Dictionary V

The process of confirming the verification process under use conditions.

JEP148, 4/04

The time interval during which a signal is (or should be) valid.

JESD100-B, 12/99

The time interval during which output data continues to be valid following a change of input conditions that could cause the output data to change at the end of the interval.

JESD100-B, 12/99

The point on the current-voltage characteristic corresponding to the second lowest current at which dvAK/diA = 0 when the gate is biased from a resistive voltage divider.

(2) (of a unijunction transistor characteristic): The point on the emitter current-voltage characteristic corresponding to the second lowest current at which dvEB1/diE = 0.

JESD77-B, 2/00

JESD77-B, 2/00

A two-terminal semiconductor device in which use is made of the property that its capacitance varies with the applied voltage.

Graphic symbols (ref. IEEE Std 315):

JESD77-B, 2/00

A measure of a characteristic for which every value within a given interval is possible.

EIA-557-A, 7/95
JESD659B, 2/07

A design-of-experiments (DOE) method of estimating the magnitude and contribution of each investigated source of variability to the total.

JEP132, 7/98

The difference among individual outputs of a process. The sources of variation can be grouped into two major classes: common causes and special causes.

EIA-557-A, 7/95

A transient voltage suppressor that is a two-terminal semiconductor device having a nonlinear voltage-current characteristic.

Graphic symbols (ref. IEEE Std 315):

JESD77-B, 2/00
VCC

See "logic power voltage".

See "output stage logic power voltage".

VDD

See "drain power voltage".

See "output stage drain power voltage".

VEE

See "emitter power voltage".

The process of confirming that the specified requirements are fulfilled, excluding reliability requirements.

JEP148, 4/04

To interrogate the internal configuration contents of a programmable logic device (PLD) to confirm that it has been correctly programmed by comparing the data in the device to that in an external file containing the desired configuration. Similar to reading except that the contents of the PLD are not transferred to the programming system.

JESD32, 6/96

A field-effect transistor in which the current between the drain and source electrodes is primarily normal to the top surface of the die.

NOTE If the device has an MOS structure, the usual abbreviation is "VMOS".

JESD24, 7/85
JESD77-B#, 2/00

A surface-mount package that is intended to be mounted perpendicular to the seating plane.

NOTE The package may include supporting posts (for insertion through the seating surface) or pedestals (for attachment to the seating surface).

JESD30D, 7/06

See "vertical field-effect transistor".

VHH

See "special function enable voltage".

See "integrated circuit, very-high-speed".

via

An electrically conducting path that passes through an insulating material and connects conducting layers in two or more planes.

JESD99B, 5/07

See "multiport DRAM".

The theoretical point or region in a simplified model of the thermal and electrical behavior of a semiconductor device at or in which all the power dissipation within the device is assumed to occur.

JESD99B, 5/07

(1) A temperature representing the temperature of the junction(s) calculated on the basis of a simplified model of the thermal and electrical behavior of the semiconductor device.

NOTE The term "virtual-junction temperature" is taken from IEC standards. It is particularly applicable to multijunction semiconductors and is used to denote the temperature of the active semiconductor element when required in specifications and test methods. The term "virtual-junction temperature" is used interchangeably with the term "junction temperature".

(2) The temperature of the virtual junction.

JESD51-1#, 12/95
JESD77-B, 2/00
JESD282-B, 4/00


JESD99B, 5/07

The control and organization of main storage to create a memory-mapping scheme that augments main storage by transferring in a block of data from mass storage whenever a portion of that block is addressed.

NOTE 1 These transfers do not require implementation by the programmer.

NOTE 2 The use of virtual memory causes mass storage to appear as part of main storage.

JESD100-B, 12/99

Deprecated synonym for "light-emitting diode".

JESD77-B, 2/00

A reference mark, chamfer, notch, tab, flat, or similar feature that identifies the number-one terminal position.

RS-308-A, 8/81

See "visible-light-emitting diode (deprecated)".

Very-large-scale integration.

JESD99B, 5/07

See "vertical field-effect transistor".

A memory in which the data content is lost when power is no longer supplied to it. (Ref. IEC 748‑2.)

JESD100-B, 12/99

The ratio of the change in voltage at the output terminal with respect to ground (or change in voltage between the output terminals) to the change in common-mode input voltage with the differential input voltage held constant.

JESD99B, 5/07

The ratio of the change in voltage at the output terminal with respect to ground (or change in voltage between the output terminals) to the change in differential input voltage with the common-mode input voltage held constant.

JESD99B, 5/07

The ratio of the change in single-ended output voltage of a differential amplifier to the change in single-ended input voltage.

JESD99B, 5/07

The time interval during which an input pulse that is switching the transistor from a nonconducting to a conducting state rises from 10% of its peak amplitude and the collector voltage waveform falls to 90% of its on-state amplitude, ignoring spikes caused by interaction with other components or parasitics, e.g., freewheeling-diode recovery current and parasitic inductance.

JESD77-B, 2/00

The time interval during which the collector (or drain) voltage changes from 90% to 10% of its peak off-state value, ignoring spikes caused by interaction with other components or parasitics, e.g., freewheeling-diode recovery current and parasitic inductance.

JESD24, 7/85
JESD77-B, 2/00

Commonly used as a synonym for "voltage amplification".

JESD99B, 5/07

A diode that is normally biased to operate in the breakdown region of its voltage-current characteristic and that develops across its terminals a reference voltage of specified accuracy when biased to operate throughout a specified current and temperature range. (Ref. IEC 747‑1.)

Graphic symbol (ref. IEEE Std 315):

JESD77-B, 2/00

A circuit or portion of a circuit that provides isolation between the load and the supply to be regulated so that the load voltage remains relatively independent of load current or input voltage fluctuations.

JESD99B, 5/07

A diode that is normally biased to operate in the breakdown region of its voltage-current characteristic and that develops across its terminals an essentially constant voltage throughout a specified current range. (Ref. IEC 747‑1.)

Graphic symbol (ref. IEEE Std 315):

JESD77-B, 2/00

The time interval during which the collector (or drain) voltage changes from 10% to 90% of its peak on-state value, ignoring spikes caused by interaction with other components or parasitics, e.g., freewheeling-diode recovery current and parasitic inductance.

JESD24, 7/85
JESD77-B, 2/00

The time interval during which an input pulse that is switching the transistor from a conducting to a nonconducting state falls from 90% of its peak amplitude and the drain voltage waveform rises to 10% of its off-state amplitude, ignoring spikes caused by interaction with other components or parasitics, e.g., freewheeling-diode recovery current and parasitic inductance.

JESD24, 7/85
JESD77-B, 2/00

The sum of voltage turn-off delay time and voltage rise time, i.e., toff(v) = td(off)v + trv.

JESD24, 7/85
JESD77-B, 2/00

The time interval during which an input pulse that is switching the transistor from a nonconducting to a conducting state rises from 10% of its peak amplitude and the drain voltage waveform falls to 90% of its off-state amplitude, ignoring spikes caused by interaction with other components or parasitics, e.g., freewheeling-diode recovery current and parasitic inductance.

JESD24, 7/85
JESD77-B, 2/00

The sum of voltage turn-on delay time and voltage fall time, i.e., td(on)v = td(on)v + tfv.

JESD24, 7/85
JESD77-B, 2/00

Synonym for "varactor diode".

JESD77-B, 2/00

The dc voltage per unit thickness, applied across two electrodes in contact with a specimen, divided by the current per unit area passing through the system.

NOTE 1 Volume resistivity is generally expressed in ohm-centimeters.

NOTE 2 When concentric ring electrodes are used as described in ASTM-D991, volume resistivity is calculated by using the following equation:

volume resistivity (rv) = π × (D1)2 × R/4T

where

D1 = diameter of inner electrode or disk;
R = measured resistance in ohms;
T = thickness of specimen.

JESD625-A, 12/99
VPP

See "programming power voltage".

See "multiport DRAM".

See "reference power supply".

VSS

See "ground reference or source power voltage (pin)".

See "output stage source power voltage or output stage ground reference (pin)".

A latch-up test that supplies overvoltage pulses to the Vsupply pin under test.

JESD78A, 2/06

All device under test power supply and external voltage source pins (excluding ground pins), including both positive- and negative-potential pins.

NOTE 1 Generally, it is permissible to treat equal potential voltage source pins as one Vsupply pin (or pin group) and connect them to one power supply.

NOTE 2 When forming Vsupply pins (or pin groups), combining Vsupply pins with significantly different supply current levels is not recommended as this would make it difficult to detect significant current changes on low-supply-current pins.

JESD78A, 2/06
VTC

The temperature coefficient of gate-emitter on-state voltage with respect to junction temperature.

JESD24-6, 10/91
VVC

See "voltage-variable-capacitance diode".

See "voltage-variable-capacitance diode".

The dc voltage between the terminal indicated by the first subscript and the reference terminal (stated in terms of the polarity at the terminal indicated by the first subscript).

JESD10, 9/81

The dc voltage between the terminal indicated by the first subscript and the reference terminal (stated in terms of the polarity at the terminal indicated by the first subscript).

JESD10, 9/81

The dc voltage between the terminal indicated by the first subscript and the reference terminal (stated in terms of the polarity at the terminal indicated by the first subscript).

JESD10, 9/81

The dc voltage between the terminal indicated by the first subscript and the reference terminal (stated in terms of the polarity at the terminal indicated by the first subscript).

JESD10, 9/81

The dc voltage between the terminal indicated by the first subscript and the reference terminal (stated in terms of the polarity at the terminal indicated by the first subscript).

JESD10, 9/81

The dc voltage between the terminal indicated by the first subscript and the reference terminal (stated in terms of the polarity at the terminal indicated by the first subscript).

JESD10, 9/81

The dc voltage between the terminal indicated by the first subscript and the reference terminal (stated in terms of the polarity at the terminal indicated by the first subscript).

JESD10, 9/81

The dc voltage between the terminal indicated by the first subscript and the reference terminal (stated in terms of the polarity at the terminal indicated by the first subscript).

JESD10, 9/81

The dc voltage between the terminal indicated by the first subscript and the reference terminal (stated in terms of the polarity at the terminal indicated by the first subscript).

JESD10, 9/81

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