Dictionary T

T1

See "terminal 1".

T2

See "terminal 2".

The free-fall drop height of the drop table needed to attain the prescribed peak acceleration and pulse duration.

JESD22-B111, 7/03

The input signal power to a circuit that produces a 6-dB signal-to-noise ratio at the output.

JESD99B, 5/07

The desired value for a statistic of a characteristic or parameter of a process node.

EIA-557-A, 7/95

The desired test-line temperature under stress.

JESD61, 4/97

The desired time it should take for the resistance of the test structure to first equal or exceed the failure resistance criterion, RFC, while the structure is under stress from the SWEAT algorithm.

JEP119A, 8/03
TCK

See "test port clock".

See "temperature coefficient of resistance".

TDI

See "test data in".

TDO

See "test data out".

A supplier's dedicated system of review that is responsible for the implementation of the quality management program, maintenance of all certified and qualified processes, process change control, reliability data analysis, failure analysis, device recall procedures, and qualification status of the technology.

JEP133B, 3/05

Acceptance testing of the surface finish material set and the manufacturing processes that include a defined set of base metals, underplating metals, surface finish alloy, surface finish bath chemistry, and process flow steps.

JESD201, 3/06

An assessment of the metrics established to evaluate technology attributes.

JEP146#, 6/03

The value of the last recorded estimated mean temperature of the test structure during the control cycle before the failure criterion, RFC, is satisfied.

JEP119A, 8/03

The change in a parameter divided by the change in temperature.

NOTE This quotient is the average value over the total temperature change. The change in the parameter may or may not be normalized to a reference value of the parameter. The specific term should be "temperature coefficient of (parameter)".

JESD77-B, 2/00
JESD99B, 5/07

The change in input bias current divided by the change in temperature.

NOTE This quotient is the average value for the total temperature change. The change in input bias current is usually not normalized to the initial value of input bias current.

JESD99B, 5/07

The change in input offset current divided by the change in temperature.

NOTE This quotient is the average value of the total temperature change. The change in input offset current is usually not normalized to the initial value of input offset current.

JESD99B, 5/07

The change in input offset voltage divided by the change in temperature.

NOTE This quotient is the average value for the total temperature change. The change in input offset voltage is usually not normalized to the initial value of input offset voltage.

JESD99B, 5/07

The change in output voltage, usually expressed as a percentage of the output voltage, divided by the change in temperature.

NOTE This is the average value for the total temperature change.

JESD99B, 5/07

The fractional change in resistance of the test structure per unit change in temperature at a specified temperature Tref, as described in the following equation:

where

R(Tref) is the resistance of the test structure at temperature Tref (Ω);
ΔR is the change in resistance (Ω);
ΔT is the change in temperature that caused the change in resistance (°C).

JEP119A, 8/03
JESD33B#, 2/04
JESD61, 4/97

NOTE 1 The letter symbol for the temperature coefficient of an analog characteristic consists of the letter symbol α with a subscript referring to the relevant characteristic, e.g., aEG for the temperature coefficient of the gain error.

NOTE 2 Temperature coefficients of analog characteristics are usually specified in "parts per million (relative to the full-scale value) per degree Celsius", that is, in "ppm/oC".

JESD99B, 5/07

The time interval between one high-temperature extreme and the next, or from one low-temperature extreme and the next.

JESD22-A105C, 1/04

An electrical parameter of a semiconductor device that varies directly with junction temperature in a linear or very nearly linear fashion.

JESD51-1, 12/95

An externally available point of connection.

NOTE The use of the term "termination" as a synonym is deprecated because that term denotes the external elements connected to the terminal.

(2) (for outline drawing purposes): That part of the package or device used primarily for making an electrical, mechanical, or thermal connection. Examples of terminals are flexible leads, rigid leads, and studs.

JESD10#, 9/81
JESD22-B108A, 1/03
JESD30D, 7/06
JESD77-B, 2/00
JESD99B, 5/07
JESD282-B, 4/00

RS-308-A, 8/81

The terminal that is designated "1" by the manufacturer.

JESD77-B, 2/00

The terminal that is designated "2" by the manufacturer.

JESD77-B, 2/00

The point on the terminal surface that exhibits the greatest perpendicular distance from the package substrate.

JESD22-B108A, 1/03

The term "terminal-to-ground capacitance" is preferred.

JESD99B, 5/07

The measurement of a parameter and the comparison to a standard.

JEP143, 5/04

The test temperature, supply voltage, current limits, voltage limits, clock frequency, input bias voltages, and preconditioning vectors applied to a device being tested.

JESD78A, 2/06

Serial scan test data input.

JESD21-C, 1/97

Serial scan test data output.

JESD21-C, 1/97

The configuration of conductors and dielectrics used to bring test signals to the device under test in a consistent manner.

JEP123, 10/95

The time interval from the beginning of a test clock cycle to the instant when an output of a device is observed and compared to an expected result.

JESD12-1B, 8/93
JESD99B, 5/07

On a memory, the input that, when true, causes built-in on-chip test logic to be actuated and the part to go into its test mode of operation.

JESD21-C, 1/97

Latch-up trigger testing of a device in a known stable state, at the minimum-rated clock frequency applied to the device.

JESD78A, 2/06

A metallization line of specified dimensions, with or without vias making connections to over- or underlying metal levels, whose length is defined by the locations of two voltage taps used to make Kelvin-type resistance measurements of the test line when two other terminals force a current through the line.

JESD33B, 2/04

The resistance of the non-joule-heated test line at any time during the test.

JESD61, 4/97

The instructions for executing a test or applying a stress.

JEP143, 5/04

A control input that enables the scan test clock and is used to select test modes.

JESD21-C, 1/97

(1) A set of test vectors.

(2) A circuit or elements processed in the semiconductor wafer to act as test sites for monitoring fabrication processes

JESD12-5, 8/88

JESD99B, 5/07

The ratio of the total number of detected faults to the total number of detectable faults.

JESD12-5, 8/88

Serial scan test clock input.

JESD21-C, 1/97

Serial scan test port reset

JESD21-C, 1/97

A test pattern and instructions suitable for use on automatic test equipment.

NOTE A test program may be used to perform functional and parametric (ac, dc, or other) tests.

JESD12-5, 8/88

The nature of the electrical signal used to measure electrical model parameters. It can be characterized by risetime, pulse shape, frequency, amplitude, etc.

JEP123, 10/95

A passive metallization structure, including a test line, that is fabricated on a semiconductor wafer by procedures used to manufacture microelectronic integrated devices.

NOTE    Connections are provided to make Kelvin-like resistance measurements of the test line, i.e., two taps for sensing voltage when two other terminals force a current through the line. Typically, these terminals are located at the ends of the test line in single-level structures, while multi-level structures have vias that connect the ends of the test line to the over- or underlying metal level in which the terminals are located.

JESD33B#, 2/04
JESD61A.01, 10/07

Creation and insertion of test circuitry to improve testability of a design.

JESD12-1B, 8/93
JESD99B, 5/07

A single instance of input stimuli and expected output responses.

JESD12-5, 8/88

A circuit or IC designed for the purpose of evaluating one or many device characteristics.

NOTE 1 For the purposes of JESD89, the characterization is the soft-error sensitivity of a particular process technology, but the test vehicle can incorporate other structures used to characterize different parameters, such as yield, speed, voltage margin, etc.

NOTE 2 This test vehicle is not typically a product but is a dedicated component or section of an IC chip designed to be used in predicting the SER of a product.

JESD89A, 10/06

A field-effect transistor having two independent gate regions, a source region, and a drain region. (Ref. IEC 747‑8.)

NOTE 1 A substrate terminated externally and independently of other elements is considered a gate for the purposes of this definition.

NOTE 2 If no confusion is likely, the term may be abbreviated to "field-effect tetrode."

JESD24, 7/85
JESD77-B, 2/00
TF

See "test function".

The change in temperature difference between two specified points or regions that occurs during a time interval divided by the step-function change in power dissipation that occurred at the beginning of the interval and caused the change in temperature difference.

JESD10#, 9/81
JESD51-1#, 12/95
JESD77-B, 2/00
JESD282-B, 4/00

The transient thermal impedance from the semiconductor junction(s) to the ambient.

JESD10, 9/81
JESD77-B, 2/00

The transient thermal impedance from the semiconductor junction(s) to a stated location on the case.

JESD10, 9/81
JESD77-B, 2/00

The transient thermal impedance from the semiconductor junction(s) to a stated location on a lead.

JESD77-B, 2/00

The transient thermal impedance from the semiconductor junction(s) to a stated location on the mounting surface.

JESD77-B, 2/00

The transient thermal impedance from the junction to a reference point. For a specified power pulse duration, ZθJX is given by

ZθJX = (TJf - TJi - ΔTX) / PH

where

TJf is the junction temperature at the end of the power pulse;

TJi is the junction temperature before the start of the power pulse;

ΔTX is the change in reference point temperature during the heating pulse. For short heating pulses, e.g., during die attach evaluation, this term is normally negligible;

PH is the magnitude of the heating power pulse applied to the device under test, i.e., the product of IH and VH.

JESD24-3, 11/90
JESD24-4, 11/90

The temperature difference between two specified points or regions divided by the power dissipation, under conditions of thermal equilibrium.

JESD10, 9/81
JESD51-1#, 12/95
JESD77-B, 2/00
JESD99B, 5/07
JESD282-B, 4/00

The thermal resistance from the device case to the ambient.

JESD77-B, 2/00
JESD99B, 5/07

(1) The thermal resistance from the virtual junction(s) of a semiconductor device to the ambient.

(2) The thermal resistance from the virtual junction(s) of a semiconductor device to a natural convection (still-air) environment surrounding the device,

JESD10#, 9/81
JESD77-B, 2/00
JESD99B, 5/07

JESD51-1#, 12/95

(1) The thermal resistance from the virtual junction(s) of a semiconductor device to a stated location on the case.

(2) The thermal resistance from the virtual junction(s) of a semiconductor device to the outside surface of the package (case) closest to the chip mounting area when that same surface is properly heat sunk so as to minimize temperature variation across that surface.

JESD10#, 9/81
JESD77-B, 2/00
JESD99B, 5/07

JESD51-1#, 12/95

The thermal resistance from the virtual junction of a semiconductor device to a defined nonstandard environment surrounding the device.

JESD51-1, 12/95

The thermal resistance from the semiconductor junction(s) to a stated location on a lead.

JESD77-B, 2/00

The thermal resistance from the virtual junction of a semiconductor device to a liquid environment surrounding the device.

JESD51-1, 12/95

The thermal resistance from the semiconductor junction(s) to a stated location on the mounting surface.

JESD10, 9/81
JESD77-B, 2/00

The thermal resistance from the virtual junction of a semiconductor device to a forced convection (moving-gas) environment surrounding the device; the gas is assumed to be air unless otherwise defined.

JESD51-1, 12/95

The thermal resistance from the virtual junction of a semiconductor device to a defined reference point within the specified environment surrounding the device.

JESD51-1, 12/95

A method to measure surface deviation using shadow moiré interference fringes as the package goes through high temperature reflow soldering.

JESD22-B112, 5/05

A temperature measurement sensor comprising two dissimilar metals intimately joined together in a bead at one end that produces a small thermoelectric voltage, corresponding to the temperature of the bead.

JEP140, 6/02

A device and/or material used in measuring the temperature of a system or the ability of systems to transfer heat.

JEP140, 6/02

A bridge circuit that produces a variable dc output from a three-phase ac input.

JESD14, 11/86

A charge-coupled device in which the direction of the charge packet flow is determined by the sequence of the three [four] [five or more] clock phases.

JESD99B, 5/07

A circuit that produces a three-phase ac output from a dc input.

JESD14, 11/86

A bus on which each output port can be placed at a logic high level or a logic low level or in a high-impedance state.

JESD12-1B, 8/93
JESD99B, 5/07

Cells or macros whose outputs can be placed in a high-impedance state and can also supply low-impedance high and low logic levels.

JESD12-4, 4/87

A bipolar output both of whose active devices can be caused to be in the off state at the same time, thus presenting a high-impedance state at the output similar to the off state of an open-circuit output.

NOTE When the active devices are not in their simultaneous off states, the output acts like a totem-pole output.

Graphic symbol (ref. ANSI/IEEE Std 91 and IEC 617‑12):

JESD99B, 5/07

The point at which a logic signal transitions from one logic state to another.

JESD65B, 9/03

The minimum linear energy transfer (LET) required to cause a single-event effect (SEE).

NOTE This minimum value may depend upon the maximum fluence utilized and may be difficult to accurately determine.

JESD57, 12/96

An acoustic microscope that transmits ultrasound completely through the sample from a sending transducer to a receiver on the opposite side.

J-STD-035, 5/99

See "acoustic data, through-transmission mode".

A semiconductor device that is capable, due to internal feedback, of assuming either of two stable states and maintaining the assumed state either with no sustained control current or voltage or at least with considerably less than that necessary to initially establish that state, and that is designed to operate as a switch for the principal or on‑state current.

NOTE 1 A thyristor is a switch that can be switched on either for only one direction of the principal current (a unidirectional thyristor) or for both directions (a bidirectional thyristor).

NOTE 2 The usual configuration is a pnpn configuration to which can be added other elements needed for additional functions.

NOTE 3 The term "thyristor" may be used for any member of the pnpn family (including devices having more than four layers) when such use does not result in ambiguity or misunderstanding. In particular, the abbreviated term "thyristor" is widely used for the reverse-blocking triode thyristor, formerly called "SCR", "semiconductor controlled rectifier", or "silicon controlled rectifier".

JESD77-B, 2/00

A two-terminal thyristor having substantially the same switching behavior in the first and third quadrants of the thyristor voltage-current characteristic.

Graphic symbol (ref. IEEE Std 315):

JESD77-B, 2/00

A three-terminal thyristor having substantially the same switching behavior in the first and third quadrants of the principal characteristic.

NOTE Usually the configuration is pnpnp or npnpn.

Graphic symbol (ref. IEEE Std 315):

JESD77-B, 2/00

A semiconductor power-control module consisting of thyristors and rectifier diodes, with the control signal(s) supplied from an external source.

JESD14, 11/86

A gate-turn-off thyristor whose rated reverse voltage is significantly lower than its rated off-state voltage.

JESD77-B, 2/00

A reverse-blocking triode thyristor that can be switched from the on state to the off state as well as from the off state to the on state by applying control signals of appropriate polarity to the gate terminal.

Graphic symbols (ref. IEEE Std 315):


JESD77-B, 2/00

A reverse-conducting triode thyristor that can be switched from the on state to the off state as well as from the off state to the on state by applying control signals of appropriate polarity to the gate terminal.

JESD77-B, 2/00

A gate-turn-off thyristor whose rated reverse voltage and rated off-state voltage are essentially equal.

JESD77-B, 2/00

A unidirectional triode thyristor whose gate terminal is connected to the n‑region nearest the anode and that is normally switched to the on‑state by applying a negative signal to the gate terminal with respect to the anode terminal.

JESD77-B, 2/00

A unidirectional triode thyristor whose gate terminal is connected to the p‑region nearest the cathode and that is normally switched to the on‑state by applying a positive signal to the gate terminal with respect to the cathode terminal.

JESD77-B, 2/00

A unidirectional diode thyristor that exhibits a blocking state in the reverse direction.

Graphic symbols (ref. IEEE Std 315):

JESD77-B, 2/00

A unidirectional triode thyristor that exhibits a blocking state in the reverse direction.

NOTE If no ambiguity is likely to occur, the term may be abbreviated to "thyristor".

Graphic symbols (ref. IEEE Std 315):

JESD77-B, 2/00

A reverse-blocking triode thyristor whose rated reverse voltage is significantly lower than its rated off-state voltage.

JESD77-B, 2/00

A reverse-blocking triode thyristor whose rated reverse voltage and rated off-state voltage are essentially equal.

JESD77-B, 2/00

A unidirectional diode thyristor that conducts large currents in the reverse direction at reverse voltages comparable in magnitude to the forward on‑state voltage.

NOTE Thyristors intended for use as surge protective devices and meeting this definition are referred to as forward-conducting rather than reverse-conducting.

Graphic symbols:

JESD77-B, 2/00

A unidirectional triode thyristor that conducts large currents in the reverse direction at reverse voltages comparable in magnitude to the forward on‑state voltage.

NOTE Thyristors intended for use as surge protective devices and meeting this definition are referred to as forward-conducting rather than reverse-conducting.

Graphic symbols:

JESD77-B, 2/00

A semiconductor power-control module consisting only of thyristors, with the control signal(s) supplied from an external source.

JESD14, 11/86

A thyristor that is intended to operate as a transient voltage suppressor.

JESD66#, 11/99
JESD77-B, 2/00

Synonym for "thyristor surge protective device".

JESD66#, 11/99
JESD77-B, 2/00

A two-terminal thyristor that can switch only when the anode voltage is positive.

JESD77-B, 2/00

A three-terminal thyristor that can switch only when the anode voltage is positive.

NOTE In this definition, a second cathode or anode terminal for connecting to the control circuit is not counted.

JESD77-B, 2/00

The voltage between the two terminals.

NOTE The polarity of the thyristor voltage (with regard to terminals 1 and 2) must be specified.

JESD77-B, 2/00

(1) In the reflective mode, the time it takes for the acoustic pulse to travel from a single transducer/receiver to the interface of interest and back.

(2) In the through-transmission mode, the time it takes for the acoustic pulse to travel from the sending transducer through the sample to the receiving transducer.

J-STD-035, 5/99

The time it takes for the resistance of the test structure to first equal or exceed the failure resistance criterion, RFC, while the structure is under stress from the SWEAT algorithm.

JEP119A, 8/03

The time it takes under specific conditions for the value of a particular parameter to reach a specified failure criterion. See also "time to target".

JESD28-1#, 9/01

The time it takes under specific conditions for the value of a particular parameter of a device to change by a specified amount or to a specified value.

JESD28-A#, 12/01
JESD60A, 9/04
JESD90, 11/04

The timing models of a set of macrocells and/or macro functions.

JESD12-1B, 8/93
JESD99B, 5/07

A pin such as clock, crystal oscillator, charge pump circuit, etc., required to place the device under test in a normal operating mode.

JESD78A, 2/06

The process of exercising the functional and timing models of a particular netlist by applying input stimuli to observe the timing responses.

JESD12-1B, 8/93
JESD99B, 5/07

Tin-based outer surface finish for external component terminations and other exposed metal.

JESD201, 3/06

The process(es) performed during the manufacture of a component to reduce the propensity for tin whisker growth by minimizing the surface finish internal compressive stress.

JESD201, 3/06
TMS

See "test mode select".

TOF

See "time-of-flight".

A program that performs a function within a design automation system.

JESD12-1B, 8/93
JESD99B, 5/07

A failure of stud, fixture, or other mechanical apparatus that prevents the execution of a tensile pull on the die.

JESD22-B109, 6/02

The process of designing a circuit hierarchically starting at the highest level followed by detailed design at a lower level.

JESD12-1B, 8/93
JESD99B, 5/07

The surface layout design of a microcircuit, applied chiefly to the preparation of the masks used in fabrication.

JESD99B, 5/07

The interface between the encapsulant and the die side of the die attach surrounding the die. (Refer to Type III in Annex A of J‑STD‑035.)

J-STD-035, 5/99

The distance between the finish surface and the tip of the whisker that would exist if the whisker were straight and perpendicular to the surface.

NOTE For tin whiskers that bend and change directions, the total axial length can be estimated by adding all of the straight subdivisions of the whisker.

JESD22-A121, 10/05

The total electric charge stored in a potential well or in a discrete region of the device.

JESD99B, 5/07

The maximum difference (positive or negative) between an analog value and the nominal midstep value within any step.

NOTE 1 If this error is expressed as a relative value, the term "relative accuracy error" should be used rather than "absolute accuracy error" or "total error".

NOTE 2 This error includes all contributions from offset error, gain error, linearity error, and the inherent quantization error.

JESD99B, 5/07

The difference (positive or negative) between the actual step value and the nominal step value for any step.

NOTE 1 If this error is expressed as a relative value, the term "relative accuracy error" should be used rather than "absolute accuracy error" or "total error".

NOTE 2 This error includes all contributions from offset error, gain error, and linearity error.

JESD99B, 5/07

The ratio, expressed as a percentage, of the rms voltage of all harmonics present in the output to the total rms voltage of the output, for a pure sine-wave input.

JESD99B, 5/07

Circuit degradation or failure resulting from radiation-induced charge trapped in insulating layers (usually oxides).

JEP133B, 3/05

The sum of static phase offset, dynamic phase offset, and phase jitter.

JESD65B, 9/03

The sum of the forward and reverse power dissipations.

JESD77-B, 2/00
JESD282-B, 4/00

The management of company resources with the exclusive focus on customer satisfaction as the means of achieving sustained financial success. It combines the efforts of all employees to develop, implement, continually assess, and improve the effectiveness of its processes and systems in support of the customers' needs.

JEP132, 7/98

The sum of delay time, rise or fall time, and ripple time. (Ref. IEC 747‑3.)

JESD99B, 5/07

A bipolar output whose active devices are so controlled that as the resistance of one increases, the resistance of the other decreases so that, according to the relative states of the two active devices, the output voltage can swing between levels approaching the two supply voltages.

NOTE 1 The term "totem-pole output", as commonly used, does not include three-state outputs.

NOTE 2 No standard qualifying symbol, as part of a graphic symbol, exists to designate the totem-pole output. In ANSI/IEEE Std 91 and IEC 617-12 these outputs are identified by the absence of a qualifying symbol.

JESD99B, 5/07
TQM

See "total quality management".

On a device having both serial and parallel access ports, the output that, when true, signifies that a transfer of data from the parallel to the serial port, in certain special transfer cycles, has been completed. In devices and modules that have multiple QSFs, the QSFs are numbered beginning with 0.

JESD21-C, 1/97

The region of a charge-transfer device within which the charge flow is confined.

JESD99B, 5/07

A gate electrode, isolated from the channel by an insulating layer or junction, to which voltage is applied in order to transfer charge.

JESD99B, 5/07

The product of the number of transfers (n) and the charge-transfer inefficiency (ε).

JESD99B, 5/07

A semiconductor microwave diode that exhibits negative resistance arising from the transferred-electron effect.

NOTE 1 The transferred-electron effect is the generation of bulk negative differential conductivity in compound semiconductor devices that have multiple energy valleys when the applied electrical field is greater than the critical value at which electrons transfer from (1) a lower energy valley in which they have greater mobility and smaller effective mass to (2) a higher energy valley in which they have smaller mobility and greater effective mass.

NOTE 2 The term "energy valley" refers to a valley in an energy-versus-momentum profile.

JESD77-B, 2/00

See "thermal impedance, (transient)".

A semiconductor device that is intended to limit voltage transients by conducting surge currents.

JESD77-B, 2/00

A semiconductor device, capable of providing power amplification, whose basic functional structure includes the series connection of a supply region, a control region, and a collection region, and whose output is a simple, continuous function of the input.

JESD10, 9/81
JESD77-B, 2/00

A transistor in which electrical conduction depends on the flow of both majority and minority carriers.

JESD99B, 5/07

A modified junction field-effect transistor, used as a constant-current source, whose gate is connected to the substrate.

NOTE The channel is formed from the epitaxial material that in other regions forms the collectors of the bipolar transistors.

JESD99B, 5/07

A semiconductor power-control module consisting of transistors and rectifier diodes, with the control signal(s) supplied from an external source.

JESD14, 11/86

A transistor in which the conduction is due entirely to the flow of majority carriers and can be varied by an electric field produced by an auxiliary source.

JESD99B, 5/07

A field-effect transistor having one or more gate electrodes that are electrically insulated from the channel.

JESD99B, 5/07

A field-effect transistor having one or more gates that form p-n junctions with the channel.

JESD99B, 5/07

A transistor having a base and two or more junctions.

Graphic symbols for triode transistors (Ref. ANSI Y32.2):

NOTE In the graphic symbols, the envelope is optional if no element is connected to the envelope.

JESD10, 9/81

A transistor whose emitter-base and collector-base junctions are formed in separate topological areas of a microcircuit and in which the charge carriers flow between these junctions in a plane parallel to the surface.

JESD99B, 5/07

An insulated-gate field-effect transistor in which the insulating layer between each gate electrode and the channel is oxide material.

JESD99B, 5/07

A semiconductor power-control module consisting only of transistors, with the control signal(s) supplied from an external source.

JESD14, 11/86

A pnp transistor formed from the base and collector regions of a normal npn bipolar transistor and the substrate.

JESD99B, 5/07

A transistor in which the electrical conduction is due entirely to the flow of majority carriers.

JESD99B, 5/07

The product of the modulus (magnitude) of the common-emitter small-signal short-circuit forward current transfer ratio, hfe, and the frequency of measurement when this frequency is sufficiently high that the modulus (magnitude) of hfe is decreasing with a slope of approximately 6 dB per octave. (Ref. IEEE Std 255.)

JESD10, 9/81

The physical region between two homogeneous semiconductor regions that have different electrical properties.

JESD77-B, 2/00

The time interval between two specified levels, one near the beginning and one near the end of the same pulse edge.

JESD99B, 5/07

The time interval between a specified high-level voltage and a specified low-level voltage on a waveform that is changing from the defined high level to the defined low level.

JESD99B, 5/07
JESD100-B, 12/99

The time interval between the specified low-level voltage and a specified high-level voltage on a waveform that is changing from the defined low level to the defined high level.

JESD99B, 5/07
JESD100-B, 12/99

A semiconductor microwave diode that, when its junction is biased into avalanche, exhibits a negative resistance at frequencies below the transit-time frequency range of the diode due to generation and dissipation of trapped electron-hole plasma resulting from the intimate interaction between the diode and a multiresonant microwave cavity.

JESD77-B, 2/00

The movement of a process in a consistently increasing or decreasing direction.

EIA-557-A, 7/95

See "data-transfer/output-enable input".

An alternative term for "thyristor, bidirectional triode".

JESD77-B, 2/00

The generation of electrostatic charges that results from the separation of two pieces of material in intimate contact, when at least one of them is an insulator.

NOTE Substantial generation of static electricity can be caused by contact and separation of two materials or by rubbing two substances together.

JESD625-A, 12/99

The duration of an applied pulse from the trigger source.

JESD78A, 2/06

A positive or negative current pulse or voltage pulse applied to any terminal under test in an attempt to induce latch-up.

JESD78B, 12/08

A field-effect transistor having a gate, a source, and a drain. (Ref. IEC 747‑8.)

NOTE If no confusion is likely, the term may be abbreviated to "field-effect triode".

JESD24, 7/85
JESD77-B, 2/00

See "test port reset".

The theoretically exact location of a feature established by basic dimensions.

JESD95-1, 3/97

A tabulation relating all output logic states to all necessary or possible combinations of input logic states for sufficient successive time intervals (tn, tn+1) to completely characterize the static and dynamic functions of the digital integrated circuit, expressed in logic states or appropriate symbols.

NOTE Contrast with "function table".

JESD99B, 5/07

Small-outline packages having gull-wing leads and whose thickness is substantially less than that of the standard SOG package. TSOP1 has the leads on the ends or short edges of the package while TSOP2 has the leads on the sides or long edges of the package. The lead pitch is often finer than that commonly used in the standard SOG package.

JESD21-C, 1/97
TSP

See "temperature-sensitive parameter".

See "thyristor surge protective device".

TSS

See "thyristor surge suppressor".

A varactor diode used for rf tuning.

NOTE This includes functions such as automatic frequency control (AFC) and automatic fine tuning (AFT).

JESD77-B, 2/00

A semiconductor diode in which quantum-mechanical tunneling leads to a region of negative slope in the forward direction of the current-voltage characteristic.

NOTE 1 The current is typically a single-valued function of voltage.

NOTE 2 In practice, the distinction between tunnel diodes and backward diodes is based on circuit application emphasis of the negative-resistance property (tunnel diode) or the low-level rectification property (backward diode).

Graphic symbol (ref. IEEE Std 315):

JESD77-B, 2/00

The sum of storage time and fall time, i.e., ts + tf.

JESD10, 9/81

The sum of delay time and rise time, i.e., td + tr.

JESD10, 9/81
TVS

See "transient voltage suppressor".

A charge-coupled device with asymmetrical potential wells that provide a unidirectional flow of charge packets under the control of two sequential clock phases.

JESD99B, 5/07

The normal environmental and/or operating ranges that the application is known to function within.

NOTE This is a subset of the application use conditions.

JEP149, 11/04

A specification showing how a rating stated at a particular temperature is reduced at higher temperatures.

NOTE 1    Derating is usually expressed graphically or in terms of derating factors (e.g., mA/°C or mW/°C).

NOTE 2    For ABDs, derating applies to ratings for peak pulse current (IPPSM), peak pulse power (PPPSM), and average power dissipation (PM(AV)).

NOTE 3    Average power ratings are derated to zero at the maximum-rated junction temperature. Peak pulse power ratings may exceed zero at the maximum-rated junction temperature.

JESD77C, 10/09
JESD210, 12/07
 

(1) A graphical portrayal of temperature experienced by an assembly as it passes through a soldering process.

(2) A graphical portrayal of the spatial temperature distribution in an oven.

JEP153,1/08

The change in mean temperature of the test line divided by the change in power dissipation in the line, as described in the following equation:

Rth = ΔT/ΔP                                   (1)

where

Rth is the thermal resistance (ºC/W);
ΔT is the change in mean temperature (ºC);
ΔP is the change in power dissipation that caused the change in mean temperature (W).

NOTE 1    It is assumed that any electromigration damage that may occur during the isothermal test does not affect the thermal resistance of the line to the first order.

NOTE 2    The thermal resistance Rth is defined assuming temperature uniformity along the test line and the linear dependence of T on P: in a plot of T versus P, Rth is the slope of the straight line. Rth is dependent on the geometry of the test structure and on the thermal conductance of between the test line and the ambient. On the other hand, because the thermal conductance of the materials in the path of the heat flow from the test structure is temperature dependent, the T-versus-P relationship is not linear; i.e., the slope of this curve will gradually decrease with increasing power dissipation. In other words, Rth is temperature dependent. Therefore, over a limited range of temperatures (typically 50 °C), the T-versus-P relationship can still be considered linear,

T = T0 + Rth ×P.                             (2)

As a consequence, a best straight-line fit of equation (2), using some measured (T, P) data pairs in this limited temperature range, can be used to estimate the thermal resistance value, Rth , and the thermal resistance intercept, T0.

JESD61A.01, 10/07

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