See "serial-access memory".

A device intended to position the samples in the proper place, keep the samples from moving during the scan, and maintain planarity.

The length of the interval during which the temperature-sensitive parameter is measured after heating power is removed.

A base-current and a collector-current condition resulting in a forward-biased collector junction.

The maximum input signal or illumination power that can be transferred with a specified degree of linearity.

(2) (for digital signal applications of a charge-transfer device): The input signal or illumination power that is required to produce full-well-capacity charge packets.

The region of the drain voltage-current characteristic curve in which a change in drain-source voltage causes a relatively small change in drain current.

The voltage between the collector and emitter terminals under conditions of base current or base-emitter voltage beyond which the collector current remains essentially constant as the base current or voltage is increased. (Ref. IEC 747‑7.)

NOTE This is the voltage between the collector and emitter terminals when both the base-emitter and base-collector junctions are forward-biased.

See "serial clock".

A methodology of design in which every bistable element is a scan cell.

A methodology of design in which some, but not all, bistable elements are scan cells.

See "surface-channel charge-coupled device".

A digital circuit designed to have significant hysteresis, i.e., the difference between the positive-going and negative-going input threshold voltages, and usually having only one input.

A buried-channel charge-coupled device that uses a Schottky barrier junction to isolate the transfer gate.

A location where material has been removed or displaced. Burnishes and rub marks where material is not displaced shall not be considered as scrapes. Tool marks in the basis metal, uniformly covered by plated or deposited metal, shall not be considered to be pits or scrapes.

The deposition of conductive, resistive, or insulating films onto a substrate by pressing pastes ("inks") through screens.

See "serial data input/output".

See "serial port enable" and "sync enable".

The reference plane that designates the interface between the package or its terminals and the surface on which it is mounted.

(2) (of a surface-mounted device): The plane formed by the three terminal apexes that exhibit the greatest perpendicular distance from the package substrate, provided that the triangle formed by those three apexes encompasses the projection of the center of gravity (CoG) of the component.

The threshold crossing of a clock signal indicating the second part of the clock cycle.

Synonym for "block".

See "single-event functional interrupt".

See "single-event latch-up".

A device whose essential characteristics are due, in whole or in part, to the flow of charge carriers within a semiconductor.

NOTE For specification purposes, a semiconductor device must be considered to be either a discrete semiconductor device or an integrated circuit.

See "junction (in a semiconductor device)".

A substance whose conductivity due to the charge carriers of both signs is normally in the range between that of metals and that of insulators and in which the charge carrier density can be changed by external means.

A semiconductor diode intended to be used for signal processing.

Graphic symbol (ref. IEEE Std 315):

(1) The degree to which a process metric or output responds to the stimulation of an input.

(2) The change in a parameter divided by the change in a circuit variable other than temperature.

NOTE This quotient is the average value over the total change of the circuit variable. The change in the parameter may or may not be normalized to a reference value of the parameter. The specific term should be "(circuit variable) sensitivity".

A logic function in which there exists at least one combination of input states for which there is more than one possible resulting combination of states at the outputs. (Ref. ANSI/IEEE Std 91.)

NOTE The outputs are functions of variables in addition to the present states of the inputs, such as time, previous internal states of the element, etc.

(1) A memory (or serial port in a multiport memory) in which data is accessed sequentially and the time for access depends on the location of the data desired. In a multiport memory, this term refers to that portion of the device that is related to the serial-access port and its associated functions.

(2) A memory in which data can be accessed only in a predetermined sequence. (Adapted from IEC 748‑2.)

On a device having a serial data access port, the pins that serve as serial data output(s) when in the read mode and as serial data input(s) when in the write mode. When the device or the serial port is not selected or enabled, the output(s) are in a floating (Z) state. When the numbering of the serial data input/outputs is significant for device operation, the serial data input/outputs are numbered beginning with 0. For devices where data bit groupings have independent control, an additional suffix "x" is applied. "x" takes the values of a, b, c, etc.

A processing mode in which two or more operations are performed sequentially or consecutively in a single device. (Adapted from ANSI X3.172.)

NOTE Contrast with parallel operation.

The input that, when true, actuates the device's serial data output circuitry.

A circuit element (usually a transistor), in series with the load, that controls the output voltage by dropping a variable portion of the input voltage.

The time interval between the instant when the analog output passes a specified value and the instant when the analog output enters for the last time a specified error band about its final value.

Synonym for "total response time".

The time interval between the instant a ramp in the reference voltage starts and the instant when the analog output value enters for the last time a specified error band about the final ramp in the output.

See "single-event upset".

See "synchronous graphics DRAM".

An optical noncontact method to measure warpage using a moiré fringe pattern resulting from the geometric interference between a flat reference grating and the projected shadow of the grating on a warped test object.

A general concept for the overall pattern formed by a distribution of values.

Internal force tangential to the section on which it acts.

(2) (applied to a BGA solder ball): The force applied to a BGA solder ball in a direction parallel to the device planar surface

A tungsten carbide, or equivalent, chisel with specific angles on the bottom and back of the tool to ensure a shearing action.

The minimum time that a dry-packed moisture-sensitive device can be stored in an unopened moisture-barrier bag (MBB) such that a specified interior bag ambient humidity is not exceeded.

A circuit having a terminating impedance sufficiently low that doubling its magnitude does not produce a change in the parameter being measured that is greater than the required accuracy of the measurement.

A fault that alters the number of nodes of a circuit by connecting two or more nodes together.

The capacitance between the output terminals (drain and source) with the gate short-circuited to the source for alternating current.

The capacitance between the drain and gate terminals with the source connected to the guard terminal of a three-terminal bridge.

The time interval between the instant when the device drive rises to 50% of its peak value and the instant when it falls to 50% of its peak value.

The load current available during the shutdown mode.

A signal that is used in such a manner that any change in magnitude of some characteristic conveys information.

NOTE The characteristic may be the amplitude, phase, frequency, etc., of a quantity such as voltage, current, impedance, etc.

A signal that is used in such a manner that changes between ranges in a finite set of nonoverlapping ranges of the magnitude of some characteristic convey information.

NOTE 1 The characteristic may be the amplitude, phase, frequency, etc., of a quantity such as voltage, current, impedance, etc.

NOTE 2 For convenience, each range of values can be represented by a single value, i.e., the nominal value.

The necessary and sufficient information about a failure that establishes a strong relationship between failure characteristics and failure mechanism. This necessary and sufficient information can include emission microscopy results, morphology data, test data, IV-curves, environmental history, etc. and therefore can be either electrical or physical in nature. The scope of application can be time-based, lot-based, package-based, design-based, etc.

An integrated circuit generated entirely by a silicon compiler.

A technology similar to metal-insulator-semiconductor (MIS) technology except that the gate is silicon instead of metal.

The technology whereby monocrystalline films of silicon are epitaxially deposited onto a single-crystal sapphire substrate to provide the basic structure for the fabrication of dielectrically isolated active and/or passive elements.

Preferred term is "first-in, first-out memory".

Acceptance of a change to a surface finish manufacturing process based upon similarity and data available from previous tin whisker technology acceptance (q.v.) and manufacturing process change acceptance (q.v.) tests.

Multiple output buffers that change state within a defined short time interval.

Synonym for "integrated circuit, single-chip".

The range of single-ended input voltage that, if exceeded at any input terminal, will cause the total harmonic distortion of the output signal resulting from the single-ended input to exceed a specified maximum value.

An event in which a single energetic-particle strike induces a localized high-current state in a device that results in catestrphic failure.

A soft error that causes the component to reset, lock-up, or otherwise malfunction in a detectable way, but does not require power cycling of the device (off and back on) to restore operability, unlike single-event latch-up (SEL), or result in permanent damage as in single event burnout (SEB).

NOTE A SEFI is often associated with an upset in a control bit or register.

An irreversible change in operation resulting from a single radiation event and typically associated with permanent damage to one or more elements of a device (e.g., gate oxide rupture).

A momentary voltage excursion (voltage spike) at a node in an integrated circuit caused by a single energetic-particle strike.

The number of events per unit fluence.

NOTE 1 Device SEU cross-section is expressed in area per device.

NOTE 2 Bit SEU cross-section is expressed in area per bit.

A multichip module in which the body has a SIP form and is made up primarily of memory devices. (See also "ZIP/SIMM".)

A model parameter determined so that the whole electrical signal path is represented by a single inductance or capacitance value. Such model parameters will generally be useful at relatively low frequencies and fail to yield acceptable simulation results as the frequency of operation is increased and the interconnect takes on a more distributed nature.

A circuit that produces a variable dc output from a single-phase ac input and a transformer with a center-tap connection.

A printed circuit board assembly with components mounted on only one side of the board.

A unipolar output whose primary connection within the integrated circuit is through an active device to the least positive (most negative) supply voltage (typically the circuit common).

NOTE 1 When the active device is in its on state, the output voltage approaches the voltage of the supply to which it is connected by the active device; when the device is in its off state, the output is pulled up to the most positive (least negative) supply voltage through the external circuit to which the output is connected.

NOTE 2 Examples of sink drivers are npn open-collector, pnp emitter-follower, pnp open-emitter, n‑channel open-drain, p‑channel open-source, and p‑channel source-follower outputs.

Graphic symbol (ref. ANSI/IEEE Std 91 and IEC 617‑12):

NOTE The bar below the diamond indicates that the output is at the low logic level when the active device is in its on state.

Synonyms for "single-in-line memory module (SIMM)".

The difference in internal delay between the individual output transitions for a given change of digital input.

NOTE The internal (as well as external) skew has a major influence on the settling time for critical changes in the digital input, e.g., a 1-LSB change from 011...111 to 100...000, and is an important source of commutation noise.

The magnitude of the time difference between two events that ideally would occur simultaneously.

The skew time between two outputs of a single integrated circuit with all driving inputs switching simultaneously and the outputs switching in opposite directions while driving identical loads.

The skew time between the controlled-edge position of two different output frequencies on a phase-locked loop (PLL) or counting device that has more than one output frequency, when both signals are rising or both signals are falling.

The skew time between specified outputs of a single logic device switching from the high level to the low level while driving identical loads.

NOTE Each input-to-output propagation delay time may be measured individually, and the difference is the skew time.

The magnitude of the difference in propagation delay times between any specified terminals of two integrated circuits at identical operating conditions.

The magnitude of the difference between the propagation delay times t_PHL and t_PLH when a single switching input causes one or more outputs to switch.

The time rate of change of the closed-loop amplifier output voltage for a step-signal input.

NOTE Slew rate is normally measured between specified output levels using the largest input voltage step for which amplifier performance remains linear with feedback adjusted for unity amplification.

The maximum rate of change of the analog output following a large step change of the reference voltage.

NOTE The abbreviation "SR(ref)" is also used.

A surface-mount package that conforms to the "small-outline" concept and has the leads formed into a "gull-wing" configuration.

A package whose chip cavity or mounting area occupies a major fraction of the package area and whose terminals are on one or two (normally opposite) sides and consist of metal pad surfaces (on leadless versions) or leads formed around the sides and under the package or extending out from the package (on leaded versions).

NOTE 1 On leaded versions, the lead form is usually gull wing but other lead forms may be used.

NOTE 2 The quad flatpack is similar except for having terminals on four sides of the package.

The small-signal resistance between drain and source terminals with a specified gate-source voltage applied to bias the device to the on-state.

NOTE For a depletion-type device, the gate-source voltage may be zero.

The ratio of the ac collector current to the small-signal ac base current with the collector short-circuited to the emitter for ac. (Ref. MIL‑S‑19500D.)

The small-signal ac base-emitter voltage divided by the ac base current with the collector short-circuited to the emitter for ac. (Ref. MIL‑S‑19500D.)

See "synchronous MPDRAM".

See "silicon-nitride-oxide-semiconductor technology".

An erroneous output signal from a latch or memory cell that can be corrected by performing one or more normal functions of the device containing the latch or memory cell.

NOTE 1 As commonly used, the term refers to an error caused by radiation or electromagnetic pulses and not to an error associated with a physical defect introduced during the manufacturing process.

NOTE 2 Soft errors can be generated from SEU, SEFI, MBU, MCU, and/or SET. The term SER, which includes a variety of soft error mechanisms, has been adopted by the commercial industry while the more specific terms SEU, SEFI, etc. are typically used by the avionics, space, and military electronics communities.

The rate at which soft errors occur.

A soft error that can be corrected by repeated reading without rewriting and without the removal of power.

The computer programs, procedures, rules, and possibly associated documentation concerned with the operation of a data processing system. (Ref. ANSI X3.172.)

NOTE 1 Contrast with "hardware" and "firmware".

NOTE 2 Computer programs stored on disks, including hard drives and CD‑ROMs, are customarily referred to as software.

See "small-outline J-lead (package)".

A discrete amount of solder attached to the metallization on a die and intended to form an interconnection to a substrate.

A fracture within the bulk of the solder bump column.

A cavity within a solder joint that exposes device or substrate metallization.

See "small-outline gull-wing (package)".

See "alpha activity (of a source)".

The direct current into the source terminal of a depletion-type transistor with a specified gate-drain voltage applied to bias the device to the off-state.

A unipolar output whose primary connection within the integrated circuit is through an active device to the most positive (least negative) supply voltage.

NOTE 1 When the active device is in its on state, the output voltage approaches the voltage of the supply to which it is connected by the active device; when the device is in its off state, the output is pulled down to the least positive (most negative) supply voltage through the external circuit to which the output is connected.

NOTE 2 Examples of source drivers are pnp open-collector, npn emitter-follower, npn open-emitter, p‑channel open-drain, n‑channel open-source, and n‑channel source-follower outputs.

Graphic symbol (ref. ANSI/IEEE Std 91 and IEC 617‑12):

NOTE The bar above the diamond indicates that the output is at the high logic level when the device is in its on state.

The dc voltage between the source terminal and the gate terminal.

The dc supply voltage applied to a circuit connected to the source terminal

A functional region in which the net charge density is significantly different from zero. (Ref. ANSI/IEEE Std 100.)

NOTE 1 The net charge is caused by electrons, holes, and ionized acceptors and donors.

NOTE 2 The space-charge regions of a semiconductor device include accumulation (enhancement), depletion, and inversion layers.

(2) (of a p‑n junction): A space-charge region contained between two neutral regions of types p and n.

The space-charge region between the functional emitter region and the functional base region.

See "statistical process control".

See "surge protective device".

A process variation outside the random or predictable pattern of the process.

A special high-voltage logic level (super voltage) that enables special on-chip functions.

A package whose outline style is not otherwise specified in JESD30.

The boundaries for judging acceptability of a particular characteristic.

A write transfer in which the SAM data register is split into two halves and the data is transferred to the RAM data bus separately after each half of the SAM register is filled.

A process in which material is physically removed from a designated surface by bombardment of ions generated in a plasma.

NOTE The gas used is generally inert or nonreactive, e.g., argon or helium.

See "serial data output".

See "statistical reliability monitoring".

See "split read transfer".

Small-scale integration.

See "sync byte 'x' select".

(1) The absence of special causes of variation; the property of being in statistical control.

(2) The measurable ability of an attribute or output of a process to remain constant within prescribed boundaries.

Synonym for "pushdown storage".

A measure of the spread or variation in a probability distribution (population standard deviation) or in a sample of values measured on the output from a process (sample standard deviation).

An integrated circuit developed and produced for multiple applications or functions and made available for multiple customers.

The supply current drawn by the regulator with no output load and no reference voltage load.

An operating mode in which all accesses to a dynamic random-access memory occur within a page boundary defined by the row address and column addresses are entered while the column address strobe remains active.

NOTE See also note to "page mode".

The dc resistance between the drain and source terminals with a specified gate-source voltage applied to bias the device to the on-state.

NOTE For a depletion-type device, the gate-source voltage may be zero.

The dc collector current divided by the dc base current. (Ref. MIL‑S‑19500D.)

The time interval between similar points on the waveforms of the averaged input reference clock and the averaged feedback input signal when the phase-locked loop (PLL) is locked and the input reference frequency is stable.

NOTE 1 PLL jitter may cause excursions of t_(φ) beyond the specified maximum.

NOTE 2 The term "PLL reference zero delay" has been used for this concept but its use is deprecated.

A volatile read/write memory in which the data is retained in the absence of control signals generated inside or outside the integrated circuit. (Adapted from IEC 748-2.)

NOTE 1 The words "read/write" may be omitted from the term when no misunderstanding is likely.

NOTE 2 A static memory can use dynamic addressing or sensing circuits.

NOTE 3 Contrast with "dynamic (read/write) memory".

A value calculated from or based upon sample data used to make inferences about a parameter of the population from which the sample came.

The conversion of data to information using statistical techniques to document, correct, and improve process performance.

A statistically based methodology for monitoring and improving reliability involving identification and classification of failure mechanisms, development and use of monitors, and investigation of failure kinetics, allowing prediction of failure rates at use conditions.

The absolute value of the difference in step values between two adjacent steps in the transfer diagram.

NOTE For companding digital-to-analog converters, the term "step size" is in general use.

A specified step value that exactly represents the corresponding digital input code.

Synonym for "wedge bond".

A gate electrode, isolated from the channel by an insulating layer or junction, to which voltage is applied in order to store charge.

The time interval from a point 90% of the maximum amplitude on the trailing edge of the input pulse to a point 90% of the maximum amplitude on the trailing edge of the output pulse.

A circuit or device into which data has been or can be entered, in which that data is or can be stored, and from which that data can be retrieved.

NOTE Examples include DRAM cells, SRAM cells, and flip-flops.

An approximation of the current versus voltage on‑state characteristic by means of a straight line that crosses this characteristic at two specified points.

The application of a forced condition that is outside of the usual operating range for some period of time.

A transistor package having all of its leads in a single plane.

NOTE This includes beam leads.

A fault in a digital circuit characterized by a node remaining at a logic high (1) state regardless of changes in input stimuli.

Synonym for "post-mount package".

A distinguishable portion of a microcircuit element.

EXAMPLE The emitter, collector, and base of an integrated bipolar transistor are subelements of an integrated circuit.

The supporting material upon which or within which the elements of a semiconductor device are fabricated or attached.

(2) (of a film integrated circuit): A piece of material forming a supporting base for film circuit elements and possibly additional components.

(3) (of a flip chip die): The supporting material upon which one or more semiconductor flip chip die are attached.

(4) (original substrate): The original semiconductor material being processed.

NOTE The original material may be a layer of semiconductor material cut from a single crystal, a layer of semiconductor material deposited on a supporting base, or the supporting base itself.

(5) (remaining substrate): The part of the original material that remains essentially unchanged when the device elements are formed upon or within the original material.

NOTE The intended meaning will usually be clear from the context in which the term is used. If necessary, distinction can be made between the "original substrate" and the "remaining substrate".

A failure found in tensile pull of flip chip solder joints, where the substrate is fractured and damaged before all the solder bumps are separated from it.

A bias voltage that maintains the substrate at a potential that is negative with respect to GND or VSS in an NMOS or CMOS part.

A letter (e.g., A, B, C), immediately following the device number, that indicates the speed grade for the device.

NOTE 1 For example, FCT244A refers to the "A" speed version of the "244" function with CMOS output swing, and FCT244AT refers to the "A" speed version of the "244" function with TTL output swing.

NOTE 2 The slowest speed grade has no such suffix.

A document that conveys to a supplier an evaluation of their performance based on criteria as defined by the customer and agreed to by the supplier.

The current into a supply terminal of an integrated circuit when the output is (all outputs are) at a low-level voltage.

The supply voltage applied to a circuit connected to the reference terminal.

The absolute value of the ratio of the change in input offset voltage to the corresponding change in value of one supply voltage with all remaining supply voltages held constant.

NOTE See the reciprocal definition under "supply voltage rejection ratio".

(2) (of a digital-to-analog converter): The change in full-scale output current (or voltage) caused by a change in supply voltage.

NOTE This sensitivity is usually expressed as the ratio of the percentage change of full-scale current (or voltage) to the percentage change of supply voltage.

A charge-coupled device in which potential wells are created at the semiconductor-insulator interface and charge is transferred along that interface.

The dc voltage between two electrodes of specified configuration that contact the same side of a material or item, divided by the current through them.

NOTE Surface resistance is expressed in ohms.

The net charge density on the surface of a semiconductor.

NOTE Both the charge density and the energy levels may be influenced by such factors as the insulation layer, surface discontinuities, chemicals, ultraviolet radiation, and electrical or magnetic fields.

Synonym for "transient voltage suppressor".

See "sync write".

A semiconductor logic device designed to connect and disconnect busses or other signals, without active drivers in the connection path.

All combinations of collector current and collector-emitter voltage that are permitted to occur during turn-off of the transistor without endangering its survival.

NOTE This information is normally presented graphically.

See "switching safe operating area".

See "sync byte (group) 'x' write".

A memory type name starting with the letter "S" where "S" means "static" as in SRAM, "serial" as in SAM, or "synchronous" as in SDRAM and SGRAM.

One of the clocked address inputs. In devices where the address order is significant, the SAn form is used with the values SA0 thru SAn, where "n" is the binary numerical order of the address or data bit.

A clocked control input that logically selects byte "x" for reads and writes. If no "x" designator is given, the signal selects all bits of the device.

A clocked control input that logically selects the RAM and removes it from power-down mode

A circuit whose changes of state are controlled by a single clock signal.

A graphics DRAM (GRAM) that has a synchronous interface.

The use of a common timing source (clock) to time circuit operations or data transfer operations.

An SRAM that has input and/or output buffers (either register or latch) that are controlled by an externally supplied clock (or clocks).

A clocked control input that enables output drivers.

A defect found in a failing electronic component that is attributed to process variation, such as a metal contact open due to a photomask problem.

The collector-emitter breakdown voltage at relatively high values of collector current at which the breakdown voltage is relatively insensitive to changes in collector current, when the base terminal is, respectively,

• open-circuited.
• short-circuited to the emitter terminal.
• returned to the emitter terminal through a specified circuit.
• returned to the emitter terminal through a specified resistance.
• returned to the emitter terminal through a specified voltage.

NOTE This is the transient voltage between the collector and emitter terminals during switching with an inductive load from a forward-biased base-emitter to one of the external conditions described above.

The collector-emitter breakdown voltage at relatively high values of collector current at which the breakdown voltage is relatively insensitive to changes in collector current, when the base terminal is, respectively,

• open-circuited.
• short-circuited to the emitter terminal.
• returned to the emitter terminal through a specified circuit.
• returned to the emitter terminal through a specified resistance.
• returned to the emitter terminal through a specified voltage.

NOTE This is the transient voltage between the collector and emitter terminals during switching with an inductive load from a forward-biased base-emitter to one of the external conditions described above.

The collector-emitter breakdown voltage at relatively high values of collector current at which the breakdown voltage is relatively insensitive to changes in collector current, when the base terminal is, respectively,

• open-circuited.
• short-circuited to the emitter terminal.
• returned to the emitter terminal through a specified circuit.
• returned to the emitter terminal through a specified resistance.
• returned to the emitter terminal through a specified voltage.

NOTE This is the transient voltage between the collector and emitter terminals during switching with an inductive load from a forward-biased base-emitter to one of the external conditions described above.

The current point at which a transistor enters its second breakdown region under ESD pulse conditions and is irreversibly damaged.

The shock and vibration experienced by an application in manufacturing, shipment, operation, and user handling (user transportation and/or regular operation).

An impulse current pulse applied simultaneously to multiple terminals of a single-chip ABD array.

See “statistical quality control”.

Statistical methods and procedures used to document and ensure compliance with requirements.

The tool that is attached to the backside of a flip chip die to perform tensile pull test.

A platform that mechanically supports a bumped silicon die within a package and electrically connects the solder bump landing pads to external terminals, using layered dielectric materials and conductive traces.

An individual or business firm that provides goods or services to another.