See "ball-grid array", "can package", "chip carrier", "chip‑scale package", "clamped package", "die-size package", "disk-button package", "dual‑in‑line package", "flange-mount package", "flatpack", "grid-array package", "in-line module", "in‑line package", "long-form package", "microelectronic assembly", "post-mount package", "press‑fit package", "press-pack", "quad flatpack", "single-in-line package", "small‑outline package", "special-shape package", "stud-mount package", "uncased chip", "vertical surface‑mount package", and "wafer-level package".

An area on a chip to which a connection can be made.

Synonym for "die-attach pad".

(1) In virtual memory, a fixed-length block that is transferred as a unit between main storage and auxiliary storage. (Adapted from ANSI X3.172.)

(2) A segment of a memory addressed by a subset of its full address field, usually with speed and/or power benefits relative to access by the full address.

The input on a page select memory that, when true, unconditionally causes the page select address register to be reset to zero and the corresponding page to be selected.

A processing mode in which operations are performed concurrently in one or more devices. (Ref. ANSI X3.172.)

NOTE Contrast with serial operation.

A measurable characteristic.

A macro function produced by a module generator.

In a circuit, a fault that results in failure to meet ac or dc specifications but does not cause functional failure.

A technique for problem-solving in which all potential problem areas or sources of variation are ranked according to their contribution.

A statistically based methodology for monitoring that results in the identification and classification of defects using predetermined boundary conditions.

The formation of an insulating layer directly over a semiconductor surface to protect the surface from contaminants, moisture, and particles.

NOTE Usually an oxide of the semiconductor is used; however, deposition of other materials is also used.

A device in which all circuit elements are passive.

An output similar to an open-circuit output except that, in addition to having an internal connection through an active device to a supply voltage, it also has an internal connection through a passive device, usually a resistor, to a second supply voltage that is more positive (less negative) than the first supply voltage.

NOTE According to the state of the active device, the output voltage can swing between levels approaching the two supply voltages.

Graphic symbol (ref. ANSI/IEEE Std 91 and IEC 617‑12):

NOTE The bar below the diamond indicates that the output is at the low logic level when the active device is in its on state.

A category assigned to Pb-free components, boards, and assemblies indicating the general family of material used for the 2^nd‑level interconnect including solder paste, lead/terminal finish, and terminal material or alloy solder balls.

A symbol that can be used in place of the phrase "Pb-free".

A charge-coupled device fabricated so that the charges stored in the potential wells are holes.

See "product or process change notice".

See "presence detect".

The highest temperature on the semiconductor chip due to power dissipation internal to the semiconductor chip.

The maximum package reflow temperature as specified in J-STD-020, depending on package dimensions and on whether the product is intended for eutectic Sn-Pb or Pb-free reflow soldering.

The peak-to-peak output noise voltage with constant load and no input ripples.

See "ripple current, percent".

The critical process and end-product parameters.

A circuit designed to interface a digital device with an external nondigital device such as a lamp, light-emitting diode, or data bus.

A component with a metal frame that provides external surface-mountable terminals located around the periphery of the body of the component.

The deviation in static phase offset, t_(φ), for a controlled edge with respect to the mean value of t_(φ) in a random sample of cycles.

The absolute value of the open-loop phase shift between the output and the inverting input at the frequency at which the modulus of the open-loop voltage amplification is unity.

A device that is intended to change its conductance as a function of incident radiant flux.

Graphic symbols:

An optocoupler whose photosensitive element is a Darlington phototransistor.

Graphic symbol:

NOTE The base regions may or may not be brought out as electrical terminals.

A photodiode that is intended to take advantage of avalanche multiplication of photocurrent.

Deprecated as a synonym for "photoemitter".

A photosensitive film used in conjunction with photolithography forming a protective mask on a wafer or substrate surface to effect selective process action (e.g., diffusion, etching, etc.).

A thyristor that is intended to be responsive to radiant energy for controlling its operation as a thyristor.

Graphic symbol:

NOTE A gate terminal may or may not be provided.

A transistor that is intended to be responsive to radiant energy.

Graphic symbols (ref. IEEE Std 315):

NOTE A base or gate terminal may or may not be provided.

A phototransistor whose collector and emitter are connected to the collector and base, respectively, of a second transistor.

Graphic symbol:

NOTE Base terminals may or may not be provided.

A physical or chemical process that ultimately results in failure.

An approach to the design and development of reliable product to prevent failure, based on the knowledge of root cause failure mechanisms.

NOTE The PoF concept is based on the understanding of the relationships between requirements and the physical characteristics of the product and their variation in the manufacturing processes, and the reaction of product elements and materials to loads (stressors) and interaction under loads and their influence on the fitness for use with respect to the use conditions and time.

The nominal center-to-center distance between adjacent pins or terminals along the side of an integrated circuit package.

A shallow surface depression or crater.

A type of semiconductor device and the process technology used to fabricate it, in which all of the p-n junctions terminate at approximately the same geometric plane on the surface of the semiconductor.

NOTE Devices using similar technologies, but having one or more diffused areas lying in a slightly different, parallel plane, are also considered planar (e.g., buried collector).

An equivalent activation energy, derived from Pareto analysis and experience using the principles of the physical relationship between stress and failure rate. It can be used to estimate sample sizes and test times.

See "programmable logic device".

A logic device that includes a phase-locked loop and may also include other logic functions, such as counters, registers, and buffers.

The ratio of the time interval between the phase-locked-loop-controlled (PLL-controlled) edge and the noncontrolled edge, to the time interval between PLL-controlled edges, expressed as a percentage (%).

In JESD65B, this concept has been replaced by the concept "static phase offset (t_(φ))".

An interface in the transition region between p‑type and n‑type materials at which the donor and acceptor concentrations are equal.

A partially closed cavity on a surface.

The collection of all possible values of a given characteristic.

The two ports in a dual-port memory device. The letter A or B is appended as a suffix to any pin that is specific to that port.

The input threshold voltage when the input voltage is rising.

A package, intended for mounting to an interconnect structure or cold plate, that incorporates a threaded stud, threaded hole, or post for that purpose.

NOTE A variety of package sizes, shapes, and external terminal forms may be used.

A property, characteristic, or occurrence that could lead to a failure, described in terms of something that can be corrected or controlled.

A physical failure mechanism that (1) has been identified through physical experimentation to exist for similar products or (2) can be linked to these products through the scientific study of the product (process) physical characteristics and the physical requirements found to be necessary for the failure mechanism to occur.

A temperature cycle in an application resulting from cycling the power on and off.

The ratio (usually expressed in dB) of (1) the signal power delivered to the load after insertion of a transducer between the source and the load to (2) the signal power that was delivered to the load when the load was connected directly to the source.

The sum of the products of the dc input currents and voltages, i.e.,V_BE · I_B + V_CE ·I_C or V_EB · I_E + V_CB · I_C.

The product of the input current and voltage in the common-emitter circuit configuration.

See "pin pitch".

See "parts per million (PPM) monitoring".

See "page reset".

The measure of natural variation of repeated measurements.

The ability to determine in advance the quantifiable output of a process (e.g., quantity, cycle time, etc.).

A prefix used with several series of TTL, CMOS, and BiCMOS devices (e.g., 74XXX and 74FCTXXX) to indicate the commercial temperature range applicable to that series.

A round or elliptical package whose mechanical mounting area is pressed into the packaging interconnect structure or cold plate for purposes of thermal and electrical connection.

Action taken to modify the management systems, practices, or procedures to prevent recurrence of the current problem and similar problems where applicable.

An output driving outside the circuit boundary.

A basic building block for a specified level of design hierarchy.

The current that is switched or controlled by the semiconductor device.

The voltage (potential difference) between the main terminals.

NOTE 1 In the case of unidirectional triode thyristors, the principal voltage is called positive when the anode potential is more positive than the cathode potential and called negative when the anode potential is less positive than the cathode potential. Thus, for these thyristors, "principal voltage" and "anode-cathode voltage" are synonymous.

NOTE 2 In the case of bidirectional thyristors, the principal voltage is called positive when the potential of main terminal 2 is more positive than the potential of main terminal 1.

The distribution of the probabilities of failure as a function of time.

NOTE The probability of failure during the interval ∆t that immediately follows the instant t₁ is given by the integral of f(t) from t₁ to (t₁ + ∆t).

A mathematical representation of a probability distribution.

The process of moving from effects to causes (special or common) to actions that improve performance.

Tools for process analysis, which include histograms, scatter diagrams, time line charts, bar charts, and control charts (for existing or modified processes).

A study that quantifies natural process variability.

The determining of relationships between process parameters and process outputs or product characteristics.

Synonym for "central processing unit".

Synonym for "flow charting".

A measurable characteristic of a process that impacts product performance but may not be measured on the product.

A gate array integrated circuit that is programmed as part of the integrated circuit manufacturing process.

NOTE Process-programmable gate arrays are characterized by the ability to inventory partially fabricated wafers prior to interconnection.

The extent to which the individual values of a process characteristic vary.

The statistically calculated probability that a product does not meet the specification for some quality characteristic.

A document sent to users describing product or process changes, the reasons for the change, and the projected impact of the change.

A methodology for tracing products, forward or backward, through the manufacturing flow to isolate materials that could be similar to product identified as having quality or reliability problems.

(1) A sequence of instructions suitable for processing. (Ref. ANSI X3.172.)

(2) To design, write, and test programs. (Ref. ANSI X3.172.)

(3) To enter data into a programmable read-only memory.

NOTE 1 Fixed programming is accomplished during manufacture of the memory, e.g., by using a mask.

NOTE 2 Field programming is accomplished after the manufacturing of the memory device is otherwise complete, e.g., by selectively blowing fuses.

NOTE 3 The programming of an electrically programmable read-only memory is accomplished by injecting electrons into the floating gates of selected cells.

The event of writing a memory cell from the programmed state to the erased state and back to the programmed state.

NOTE This event may be used as a unit of measurement for endurance. Within a sequence, program-erase cycles are indistinguishable from erase-program cycles.

(1) An integrated circuit consisting of an array of combinational logic elements (circuits) with a fixed interconnection pattern in which connections can be made or broken after manufacture to perform specific logic functions. (Ref. IEC 748‑2.)

NOTE The PLA is typically a large set of AND gates driving several OR gates.

(2) A cell that emulates a programmable logic array that has been programmed in a custom integrated circuit.

(1) An integrated circuit consisting of an array of combinational and sequential logic elements (circuits) with a fixed interconnection pattern in which connections can be made or broken after manufacture to perform specific logic functions.

(2) A cell that emulates a programmable logic sequencer that has been programmed in a custom integrated circuit.

A three-terminal thyristor that, when biased with two external resistors and a voltage source, can provide a negative-resistance characteristic similar to the characteristic of a unijunction transistor.

NOTE The negative-resistance characteristics are controlled by the resistor and voltage values.

Graphic symbol:

PUT with bias resistors

NOTE B1, B2, and E are the equivalent unijunction terminals with interbase resistance r_BB = R₁ + R₂ and intrinsic standoff ratio η = R₁/(R₁ + R₂).

A special high-voltage supply that supplies the potential and energy for altering the state of certain nonvolatile memory arrays. On some devices, the presence of VPP also acts as a program enable signal (P).

A raised portion of a surface indigenous with the parent material.

The time interval between specified reference points on the input and output voltage waveforms with the output changing from one defined level (high or low) to the other defined level.

NOTE All of the response times (i.e., access, disable, enable, sense recovery, and output data-valid times) are subsets of propagation times. As integrated circuits have become more complex, the response times have been broken down into more and more specialized subgroups.

The time interval between the specified reference points on the input and output voltage waveforms with the specified output changing from the defined low level to the defined high level.

NOTE In IEC 748‑2, the reference points on both the input and output waveforms have the same value, which is midway between the maximum low-level input voltage (V_ILmax) and the minimum high-level input voltage (V_IHmin).

A layer of insulating material applied over the circuit elements for the purpose of mechanical and environmental protection and prevention of contamination.

(1) A combinational form of a dynamic RAM that incorporates various refresh and control circuits on-chip (e.g., refresh address counter and multiplexer, interval timer, arbiter). These circuits allow the PSRAM operating characteristics to closely resemble those of an SRAM.

(2) A random-access memory whose internal structure is a dynamic memory with refresh control signals generated internally, in the standby mode, so that it can mimic the function of a static memory.

NOTE In practice, unlike so-called self-refresh DRAMs, PSRAMs have nonmultiplexed address lines and pinouts similar to those of SRAMs.

See "pseudostatic random-access memory".

The time interval between the instant when the acceleration first reaches 10% of its specified peak level and the instant when the acceleration first returns to 10% of the specified peak level after having reached that peak level.

The time interval between a reference point on the leading edge of a pulse waveform and a reference point on the trailing edge of the same waveform.

NOTE The two reference points are usually 90% of the steady-state amplitude of the waveform existing after the leading edge, measured with respect to the steady-state amplitude existing before the leading edge. If the reference points are 50% points, the symbol t_w and the term "average pulse duration" should be used.

Pulse time symbology

See preferred term "pulse duration".

Synonym for "pushdown storage".

(1) Two open-circuit outputs operating in complementary fashion so that as the resistance of one increases, the resistance of the other decreases

(2) Originally a synonym for "totem-pole output", this usage is now deprecated.

NOTE The term "push-pull output" is usually applied to linear circuits.

See "pseudo write transfer".

A fracture between the passivation and the solder underbump metallurgy (UBM).

A symbol that can be used in place of the phrase ‘‘Pb-free’’.