The ability to determine the logic state(s) of a node at the circuit's externally accessible node(s).

See "output enable".

The difference between the actual midstep [step] value and the nominal midstep [step] value at the offset point.

NOTE See notes 1, 2, and 3 under "gain error".

The current into a circuit node when the device or a portion of the device affecting that circuit node is in the off state.

NOTE When additional subscripts are used, the off-state current is identified by "off" in parentheses following the additional subscripts, e.g., I_O(off) for off-state output current.

The region of the drain voltage-current characteristic curve in which a change in drain-source voltage causes a proportional change in drain current.

The small-signal impedance between the terminals through which the principal current flows when the thyristor is in the on state. (Ref. EIA‑397.)

The gate charge necessary to reach a gate-source voltage that will support a minimum specified on-state drain current.

The resistance between specified terminals with input conditions applied that, according to the product specification, will establish minimum resistance (the on-state) between those terminals.

A circuit having a terminating impedance sufficiently high that halving its magnitude does not produce a change in the parameter being measured that is greater than the required accuracy of the measurement.

The capacitance measured across the input terminals (emitter and base) with the collector open-circuited for ac. (Ref. IEEE Std 255.)

A unipolar output whose only connection within the integrated circuit is through an active device, usually a transistor, to one of the supply voltages.

NOTE 1 For the purpose of this definition, the presence of any parasitic components and freewheeling, flyback, and clamp diode is ignored.

NOTE 2 When the active device is in its on state, the output voltage approaches the voltage of the supply to which it is connected (through the active device); when the device is in its off state, the output impedance to any other terminal of the integrated circuit is high and the output voltage is determined by the external circuit to which the output is connected.

NOTE 3 Outputs of this generic class are usually classified according to the name of the element of the active device to which they are connected within the integrated circuit, e.g., open-collector output, open-drain output, etc.

NOTE 4 For graphic symbols, see "sink driver" and "source driver".

An open-circuit output whose internal connection is to the collector of a bipolar transistor.

NOTE For graphic symbols, see "sink driver" (for npn) or "source driver" (for pnp).

An output buffer that has one low-impedance output logic level and a high-impedance output state.

An open-circuit output whose internal connection is to the emitter of a bipolar transistor.

NOTE For graphic symbols, see "source driver" (for npn) or "sink driver" (for pnp).

The length of time that a device is expected to function at or below the failure rate, stated in power-on hours (POH).

A line about which the radiant-energy or sensitivity pattern is centered. (Ref. IEC 747‑5.)

NOTE 1 The radiant-energy or sensitivity pattern may be nonsymmetrical.

NOTE 2 The optical axis may deviate from the mechanical axis.

The process by which a given logic representation is reduced to a superior equivalent functional representation with respect to some system or chip-level design objective such as speed, device utilization, level of logic, etc.

An optoelectronic device designed for the transformation of electrical signals by utilizing optical radiant energy to provide coupling with electrical isolation between the input and the output. (Ref. IEC 747‑5.)

An incident where outlier product significantly impacts customer reliability.

The end result of a process that is dependent on the input.

An output current in a region of relatively low differential resistance that serves to limit the voltage swing.

The input that, on some devices containing an output data register, causes the data to be set into the register.

A control input to an integrated circuit that, depending on the logic level applied to it, either permits or prevents the output of data from the device.

NOTE When disabled, the outputs assume a low level, a high level, or a floating (high-impedance) state, depending on the design of the particular circuit.

(2) (of a memory) [pin name G(n); OE(n)]: the input that, when false, disables the outputs and causes them to go to an inactive state but does not affect the writing function.

NOTE When disabled, the inactive state is floating (Z, high-impedance) for MOS and TTL devices, and low (L) for ECL devices. In modules that have multiple OEs, the OEs are numbered beginning with 0.

An analog signal input that sets the output buffer impedance and the operating mode.

The small-signal impedance between one output terminal of a differential amplifier and ground with the other output terminal ac-grounded.

The rms output noise voltage with constant load and no input ripples.

A device pin that generates a signal or voltage level as a normal function during the normal operation of the device.

NOTE Output pins, though left in an open (floating) state during testing of other pin types, are latch-up tested.

The power pin that is intended to supply power to the output transistors of the device to provide the potential and energy to drive the load applied to the data output (Q) pins or data input/output (DQ) pins. Other, non-data, output transistors may also be designated to be supplied by this power pin. The potential of VDDQ may be specified the same as or different from that of the primary device power pins (VDD).

The ground reference voltage for the data output (Q) or input/output (DQ) pins. Other, non-data, output transistors may also be designated to be referenced to this ground pin. Internal to the device, this pin shall be dc-isolated from the primary ground reference (VSS) pin and any other ground reference pin. External to the device, it must be dc‑common with the primary ground reference.

The change in output voltage, usually expressed as a percentage of output voltage, over a period of time.

The average noise figure of the cascaded combination of a mixer and an IF amplifier.

A charge-coupled device formed so that adjacent transfer gates overlap and are insulated from one another.

The time interval required for an amplifier to recover its ability to perform amplification within stated specification limits after the output voltage amplitude has been distorted by the application of a specified input voltage in excess of rated amplitude or rated rate of change.

An oxide layer formed on a surface by methods not requiring the substrate to participate in the reaction.

NOTE Various methods such as pyrolysis, evaporation, or sputtering may be employed.

A sharp variation of the plane of the oxide on the surface of a planar device.

A physical defect that is not correlated with a known process, equipment, or procedure and cannot be described by a probability-density function of time or location.