See "lot acceptance rate".

The product of the large-signal ac output current and voltage in the common-emitter circuit configuration.

A PROM that contains a latch register for the output data.

A state in which a low-impedance path, resulting from an overstress that triggers a parasitic thyristor structure, persists after removal or cessation of the triggering condition.

NOTE 1 The overstress can be a voltage or current surge, an excessive rate of change of current or voltage, or any other abnormal condition that causes the parasitic thyristor structure to become regenerative.

NOTE 2 Latch-up will not damage the device provided that the current through the low-impedance path is sufficiently limited in magnitude or duration.

A surface region of a semiconductor device whose conductivity type is the same as that produced by the net fixed charge density of ionized donors and acceptors and whose net carrier density is higher than that necessary for neutralization due to charge carrier attraction.

NOTE The charge carrier attraction may be caused by a field-plate voltage such as in field-effect transistors or by unwanted charge residing in surface states, insulating layers, or surface ionic species.

A region whose conductivity type on each side of the junction is the same as that produced by the net fixed charged density of ionized donors and acceptors but whose net carrier density is insufficient for neutralization due to the built-in potential barrier of the p-n junction and, if present, an applied reverse bias.

(2) (associated with a surface): A surface region of a semiconductor device whose conductivity type is the same as that produced by the net fixed charge density of ionized donors and acceptors but whose net carrier density is insufficient for neutralization due to charge carrier attraction.

NOTE The charge carrier attraction may be caused by a field-plate voltage such as in field-effect transistors or by unwanted charge residing in surface states, insulating layers, or surface ionic species.

Synonym for "accumulation layer".

See "lower byte enable".

See "load color register".

A device at least 90% of whose internal power losses are dissipated )by thermal conduction through the leads to the mounting connections.

The imaged area that extends from the outer leadframe edges of the package to the leadframe "tips" (the wedge-bond/stitch-bond region of the innermost portion of the leadframe). (Refer to Type V in Annex A of J-STD-035.)

A plane perpendicular to the terminal leads that may be coincident with the seating plane or located at a defined distance from it. The locations of the terminals are measured at the gauge plane.

A feature of size that contains the least amount of material, e.g., minimum shaft diameter or maximum hole diameter.

See "linear energy transfer" and also "effective LET" and "threshold LET".

A set of circuit cells including their design parameters.

A diode capable of emitting luminous energy resulting from the recombination of electrons and holes. (Ref. IEC 747‑5.)

Graphic symbol (ref. IEEE Std 315):

An analog-to-digital converter having steps ideally of equal width excluding the steps at the two ends of the total range of analog input values.

NOTE Ideally, the width of each end step is one half the width of any other step.

A digital-to-analog converter having steps ideally of equal height.

The drain-to-source voltage for linear region measurements.

The difference in the accuracy/bias values through the expected operating range of the gauge.

The difference between the actual step value and the nominal step value after offset error and gain error have been adjusted to minimize the magnitude of the extreme values of this difference.

NOTE For a uniformly curved transfer diagram, the extreme values will be very close to half of the magnitude of the end-point linearity error.

The difference between the actual analog value at the transition between any two adjacent steps and its ideal value after offset error and gain error have been adjusted to zero.

NOTE 1 The shortened term "linearity error" is commonly used and is sufficient if no ambiguity with the term "best-straight-line linearity error" is likely to occur.

NOTE 2 The inherent quantization error is not included in the linearity error of an analog-to-digital converter. The ideal value for the transition corresponds to the nominal midstep value ±½ LSB.

A circuit designed for driving a data transmission line.

The change in output voltage, usually expressed as a percentage of output voltage, for a change in input voltage.

The format in which the least significant bit of a word is transferred first and the most significant bit is transferred last.

A nonmemory cycle in which the color register is loaded with a new value for use in subsequent special cycles that utilize its contents.

The change in output voltage, usually expressed as a percentage of output voltage, for a change in load current.

A nonmemory cycle in which the write mask register is loaded with a new value for use in subsequent masked write cycles.

The envelope established by the combined effects of tolerance of size or form and location. Two such conditions exist.

a) outer locus (OL)

1) For a male feature, the worst-case (largest) boundary or envelope of the outer surface of the feature as it moves around the tolerance zone of position.

OL = MMC + positive tolerance

2) For a female feature, the worst-case (largest) boundary or locus formed outside of the surface of the feature as it moves around the tolerance zone of position.

OL = LMC + positive tolerance

where MMC is maximum material condition and LMC is least material condition.

b) inner locus (IL)

1) For a male feature, the worst-case (smallest) boundary or locus formed inside the surface of the feature as it moves around the tolerance zone of position.

IL = LMC - positive tolerance

2) For a female feature, the worst-case (smallest) boundary or envelope of the inner surface of the feature as it moves around the tolerance zone of position.

IL = MMC - positive tolerance

A circuit configuration in which the output of a logic circuit controls an input signal to the same circuit.

A level within the more positive (less negative) of the two ranges of logic levels chosen to represent the logic states.

NOTE 1 For digital devices, the maximum value of the high logic level voltage is used for latch-up testing.

NOTE 2 For nondigital devices, the maximum operating voltage that can be applied to that pin as defined in the device specification is used for latch-up testing.

A circuit used to convert logic voltage levels of one family to corresponding logic levels of another family, such as from ECL to TTL.

(1) The more positive of the two logic supply voltage pins. The name VCC is used for the memory device supply voltage pin when the supply voltage is nominally 5 V.

(2) The ground reference power supply voltage for ECL interface devices.

One of two possible abstract states that may be taken on by a logic (binary) variable. (Ref. ANSI/IEEE Std 91.)

The part of a processor that performs logic operations. (Ref. IEC 824.)

A cylindrical or elliptical tubular package having terminal endcaps or axial leads.

A high-speed carry procedure in which a group of carry digits is formed in parallel from the respective input bits of the two groups that are to be added and, if it exists, from the most significant carry digit that immediately precedes those groups. (Ref. IEC 824.)

An estimate of the probability of lot acceptance under the sampling plan, i.e., the probability that the sample contains no more than the "accept number" of nonconforming components.

On word-wide devices, an input that, when true, enables the lower byte data input/outputs, pins DQ0 through DQ7.

A frequency-dependent electrical model parameter value asymptotically projected to very low frequency, at which various high-frequency phenomena (e.g., skin effect in the lead, parasitic coupling to neighboring elements, effects of capacitance in inductors and inductance in capacitors) have negligible effect. Such a value is often used in single-lump models.

The current into an input terminal when a specified low-level voltage is applied to that input.

The least positive (most negative) value of low-level input voltage for which operation of the logic element within specification limits is to be expected.

The voltage level at an output terminal with input conditions applied that, according to the product specification, will establish a low level at the output.

See "latched PROM".

A transferred-electron diode similar to the Gunn diode except that it is intended to operate at frequencies that are determined by the microwave cavity in which the diode is mounted and that are several times higher than the transit-time frequency so that the formation of charge packets (or domains) is limited.

NOTE Compared to the Gunn diode, higher output power at higher frequency is achievable.

Large-scale integration.

See "lower byte write enable".

A mark, on a device, created by using a laser to ablate or melt the device surface, to bond a contrasting labeling material, or to activate a pigmented coating.

The ability of a character or symbol to be read or deciphered.

A map of the positions where devices are placed for testing within the working area.