Dictionary I

I2t

The product of the square of the rms current and the time for an on-state (or forward) nonrepetitive surge current not exceeding 10 ms in duration for a single discrete element.

JESD14, 11/86
IC

See "integrated circuit".

In the transfer diagram, a straight line between the specified points for the most positive (least negative) and most negative (least positive) nominal midstep [step] values.

NOTE The ideal straight line passes through all the points for nominal midstep [step] values.

JESD99B, 5/07

A group of output terminals nominally used to convey information about the configuration or other attributes of the device when plugged into a system. The function of these outputs is similar to those of the PD(n) terminals, but the latter often have different electrical interface characteristics.

JESD21-C, 1/97

See "identification".

See "insulated-gate bipolar transistor".

See "insulated-gate field-effect transistor".

To place a device in a chain into a "bypass" mode, meaning that no operations are performed on that device. This would be done if devices in a chain were to be selectively programmed, for example.

JESD32, 6/96

The density of the luminous flux incident on a surface, i.e., the luminous flux divided by the area of the illuminated surface.

JESD77-B, 2/00

The ac collector current divided by the out-of-phase (imaginary) component of the small-signal collector-emitter voltage with the base terminal open-circuited to the emitter for ac.

JESD10#, 9/81

The out-of-phase (imaginary) component of the small-signal ac base-emitter voltage divided by the ac base current with the collector terminal short-circuited to the emitter terminal for ac.

JESD10#, 9/81

A semiconductor microwave diode that, when its junction is biased into avalanche, exhibits a negative resistance over a frequency range determined by the transit time of charge carriers through the depletion region.

JESD77-B, 2/00

The circuitry used to prevent writing from occurring when the control signals of the memory enter an indeterminate state during power on, power off, or noise transients.

JESD100-B, 12/99

The area in which a portion or all of the visual or mechanical indexes must lie.

RS-308-A, 8/81

A single unit or a single measurement of a characteristic.

EIA-557-A, 7/95

A diode capable of emitting radiant energy in the infrared region of the spectrum as a result of the recombination of electrons and holes. (Ref. IEC 747‑5.)

JESD77-B, 2/00

Synonym for "built-in electric field".

JESD77-B, 2/00

A control input that provides a preassigned manufacturer- or user-defined code to be set into the data register. If the code is all 0s, it can be called "clear", and if all 1s, then "preset".

JESD21-C#, 1/97

A control input that provides a preassigned manufacturer- or user-defined code to be presented to the data register for subsequent setting by a clock input. If the code is all 0s, it can be called "clear", and if all 1s, then "preset".

JESD21-C#, 1/97

A microelectronic assembly whose terminals consist of metal pad surfaces located on one or both sides of a circuit board designed for insertion into an edge connector.

JESD30D, 7/06

A package having a single row or parallel rows of leads designed primarily for insertion (through-hole) mounting perpendicular to the seating plane.

NOTE The leads may emerge from a single side or from two parallel sides with the leads formed to produce parallel rows.

JESD30D, 7/06

A parameter that characterizes the product prior to the finished product stage.

EIA-599-A, 6/98

An input that controls the activation of both input and output circuitry, normally storage registers or latches.

JESD21-C, 1/97

The current into the input or the average of the currents into the inputs when the device is in the quiescent or balanced state.

JESD99B, 5/07

Cells or macros that accept inputs from sources external to the integrated circuit and produce outputs to cells or macros internal to the integrated circuit.

JESD12-4, 4/87

An input current in a region of relatively low differential resistance that serves to limit the voltage swing.

JESD99B, 5/07

An input voltage in a region of relatively low differential resistance that serves to limit the voltage swing.

JESD99B, 5/07

The input that, on devices that contain input buffer registers, causes the address on the A(n) pins, the data on the D(n) pins, and/or certain control inputs to be set into the register.

JESD21-C, 1/97

The current at the input terminals.

JESD14, 11/86

The parallel equivalent of the small-signal impedances between each input terminal of a differential amplifier and ground.

JESD99B, 5/07

The small-signal impedance between two ungrounded input terminals of a differential amplifier.

JESD99B, 5/07

The small-signal impedance between one input terminal of a differential amplifier and ground with the other input terminal ac-grounded.

JESD99B, 5/07

The load (usually specified in unit loads) represented by a given input.

JESD12-1B, 8/93
JESD99B, 5/07

The difference between the currents into the input terminals of a differential-input device in the balanced state.

JESD99B, 5/07

The dc voltage that must be applied between the input terminals to force the quiescent dc output voltage to zero or other specified level.

JESD99B, 5/07

A generic term for an otherwise undefined signal pin that can operate as either an input or an output. This term is not used as a specific pin name but only as a generic indicator of the nature of the function of the pin.

JESD21-C#, 1/97

A control signal, used primarily on SDRAMs, that acts as a mask for reading and writing functions. In some instances, the DQM term includes a prefix "U" or "L" indicating upper or lower byte control. In devices where more than two data bit groupings have a data mask applied, an "x" is applied, where "x" takes the values of a, b, c, etc.

JESD21-C, 1/97

The difference between the input voltage and the output voltage.

JESD99B, 5/07

All address, data-in, control, Vref, and similar pins.

JESD78A, 2/06

An input voltage in a region of relatively low differential resistance that serves to limit the voltage swing for the purpose of input protection.

JESD99B, 5/07

The small-signal resistance between an input terminal and ground or between differential input terminals.

JESD99B, 5/07

The substantive and quantifiable attributes or input of a process model that, when combined into a common process or methodology, can be utilized to simulate the desired output.

JEP132, 7/98

The input voltage level that, when crossed, enables an output to change its logic state.

JESD99B, 5/07

Variables or steps that can alter, enhance, and/or validate a process.

JEP132, 7/98

The voltage at the input terminals.

JESD14, 11/86

The supply voltage to be regulated.

JESD99B, 5/07

The assessment of a characteristic and its comparison to a standard. Examples of inspections include low-temperature electrical tests, room-temperature tests, and visual inspection.

EIA-557-A#, 7/95
JESD16-A, 4/95

The additional error caused by the ageing of the components and specified for a relatively long period of time.

JESD99B, 5/07

The rate at which devices are failing referenced to the survivors (not to the initial number of units).

NOTE h(t) = f(t)/R(t).

JESD85, 7/01

A register that is used to hold an instruction for interpretation. (Ref. IEC 824.)

JESD100-B, 12/99

All the instructions that can be executed by a given microprocessor.

JESD100-B, 12/99

A three-terminal (collector, emitter, and gate), four-layer (pnpn/npnp) semiconductor device with an MOS-gated channel connecting the two n‑type regions (for n‑channel types), or the two p‑type regions (for p‑channel types), and in which the conductance of the high-resistance collector region is modulated (enhanced) by the injection of minority carriers from an opposite-polarity semiconductor region adjacent to the collector and opposite the channel region.

NOTE 1 The IGBT is a compound semiconductor structure with input characteristics similar to those of a vertical power MOSFET, but containing an additional bipolar component that conductivity-modulates the drain region of the MOSFET section.

NOTE 2 The conductivity modulation of the vertical DMOS power MOSFET drain region substantially reduces the inherent rise in collector-emitter resistance that results with increasing collector-emitter voltage capability.

NOTE 3 The IGBT is similar in basic structure to an MOS-gated thyristor but exhibits a fundamental operational difference in that it maintains gate control, i.e., it does not latch, over a wide range of collector current and collector-emitter voltage.

NOTE 4 The term "insulated-gate bipolar transistor" (IGBT) is the generic name for the entire class of conductivity-enhanced MOS-gated pnpn/npnp devices. Other names used to identify these types of devices include conductivity-modulated field-effect transistor (COMFET), gain-enhanced MOS field-effect transistor (GEMFET), insulated-gate transistor (IGT), and insulated-gate rectifier (IGR).

Insulated-gate bipolar transistor graphic symbols (ref. IEC 617-5):

NOTE In the graphic symbols, the envelope is optional if no element is shown connected to the envelope.

JESD77-B, 2/00

A field-effect transistor having one or more gate electrodes that are electrically insulated from the channel. (Ref. IEC 747‑8.)

JESD24, 7/85
JESD77-B, 2/00

A material having a surface resistivity of at least 1x1012 ohms per square or volume resistivity of at least 1x1011 ohm-centimeters.

JESD625-A, 12/99

A circuit in which all or some of the circuit elements are inseparably associated and electrically interconnected so that it is considered to be indivisible for the purposes of construction and commerce. (Ref. IEC 748-1.)

NOTE 1 JEDEC and IEC standards on semiconductor integrated circuits generally refer to integrated circuits that are designed as microcircuits.

NOTE 2 To further define the nature of an integrated circuit, additional qualifiers may be prefixed. Examples include

- single-chip integrated circuit,
- multichip integrated circuit,
- thin-film integrated circuit,
- thick-film integrated circuit,
- hybrid film integrated circuit, and
- hybrid semiconductor integrated circuit.

JESD99B, 5/07

A hybrid film integrated circuit in which at least one circuit element is active.

JESD99B, 5/07

A type of linear integrated circuit intended to be used so that the output is a continuous mathematical function of the input.

NOTE An operational amplifier is an example of an analog integrated circuit.

JESD99B, 5/07

See "application-specific integrated circuit".

A digital integrated circuit limited to two logic states at each of its input and output terminals.

NOTE The high-impedance state of a three-state output is not considered to be a logic state.

JESD99B, 5/07

See "custom integrated circuit".

A type of integrated circuit that is intended to accept particular logic states, changes between logic states, or sequences of logic states at its input terminals, and convert these to logic states at its output terminals according to a set of logic equations or function tables.

JESD99B, 5/07

An integrated circuit whose circuit elements, including the interconnections, are extclusively film elements formed on the surface of an insulating substrate.

JESD93#, 9/05
JESD99B, ?/06

An integrated circuit that contains two or more of a single type or a combination of types of the following elements, with at least one of the elements being active: film microcircuit, monolithic microcircuit, discrete semiconductor device, passive chip, or passive element printed or deposited on a substrate.

JESD93, 9/05

A film integrated circuit in which the main parts of the circuit elements are produced as film elements on a substrate and that is completed by mounting additional components on the substrate or elsewhere in the package.

JESD99B, 5/07

A semiconductor integrated circuit in which the main parts of the circuit elements are produced as semiconductor circuit elements and that is completed by mounting additional components in the package.

JESD99B, 5/07

An integrated circuit that accomplishes the linkage of two systems or parts of a system that would otherwise be incompatible.

NOTE The signals present at the inputs and the outputs of the interface integrated circuit may take any one of the following forms:

a) digital inputs, analog outputs;

b) analog inputs, digital outputs;

c) analog inputs, analog outputs; or

d) digital inputs, digital outputs. (In this case, the levels of the digital signals at the inputs and the outputs are dissimilar.)

Some circuits of types a, b, and c may also be classified as linear integrated circuits.

JESD99B, 5/07

Through common usage, an integrated circuit that is not purely digital.

NOTE Some circuits of this type may also be classified as interface integrated circuits.

JESD99B, 5/07

Deprecated synonym for "integrated circuit, single-chip".

JESD99B, 5/07

A semiconductor integrated circuit containing two or more chips (dice).

NOTE The use of the term "polylithic semiconductor integrated circuit" is deprecated.

JESD99B, 5/07

A hybrid film integrated circuit in which all circuit elements are passive.

JESD99B, 5/07

A semiconductor device designed as an integrated circuit.

JESD99B, 5/07

An integrated circuit or microcircuit consisting exclusively of elements formed in situ on or within a single semiconductor substrate with at least one of the elements formed within the substrate.

JESD99B, 5/07
JESD93, 9/05

A film integrated circuit whose circuit elements are thick-film elements.

JESD99B, 5/07

A film integrated circuit whose circuit elements are thin-film elements.

NOTE Usually, thin-film elements are formed by vacuum-deposition techniques, possibly supplemented by other deposition techniques.

JESD99B, 5/07

An integrated circuit meeting the following goals for speed and density established by the U.S. Department of Defense:

Phase 1 goals

product of operating frequency
and equivalent gate density 5 × 1011 Hz×gates/cm2 minimum

clock frequency 25 MHz minimum

Phase 2 goals

product of operating frequency
and equivalent gate density 1 × 1013 Hz×gates/cm2 minimum

clock frequency 100 MHz minimum

JESD99B, 5/07

The deliberate use in the formulation of a product or subpart where its continued presence is desired to provide a specific characteristic, appearance, or quality.

JIG101, 5/05

The manual modification or influence used in the pattern layout, cell placement, or interconnect routing in an otherwise automatic layout tool.

JESD12-1B, 8/93
JESD99B, 5/07

The capacitance per unit length attributable to a specified interconnection layer.

JESD12-1B, 8/93
JESD99B, 5/07

A conductive layer used for electrical interconnection of circuit elements on an integrated circuit.

JESD12-1B, 8/93
JESD99B, 5/07

A failure found in tensile pull of flip chip solder joints, where any portion of the fracture surface occurs at an intermetallic formed between the solder and the device or substrate metallization.

JESD22-B109, 6/02

Cells or macros that communicate only with other cells or macros on the same cell-based integrated circuit.

JESD12-4, 4/87

The electric field due to the presence of space charges in the transition region.

NOTE This field is dependent on the impurity profile of the transition region and on the bias applied between the two adjacent neutral regions.

JESD77-B, 2/00

An electromagnetic pulse generated by electrons that are ejected from the surfaces interior to an enclosure with conducting walls due to the interaction of a pulse of energetic photons with the surface material(s).

JEP133B, 3/05

Synonym for "virtual-junction temperature".

JESD99B, 5/07

A suspension of a process, such as the execution of a computer program, caused by an event external to that process and performed in such a way that the process can be resumed. (Ref. IEC 824.)

JESD100-B, 12/99

A central processing unit (CPU) feature that allows the computer to ignore (mask) an interrupt request until the mask bit is disabled.

JESD100-B, 12/99

An external signal that requests a temporary suspension of the normal program operation in order to permit processing of a higher-priority operation.

NOTE Multiple interrupt capability requires establishment of an interrupt-priority system.

JESD100-B, 12/99

(1) A failure mechanism caused by a natural deterioration in the materials or by the manner in which the materials are combined during fabrication or assembly processes that are within specification limits.

(2) A failure mechanism attributable to natural deterioration of materials processed per specification.

JESD659B, 2/07
I/O

See "I/O (bidirectional) pins" and "input/output".

A device pin that can be made to operate as an input or an output or in a high-impedance state.

JESD78A, 2/06

A method for doping semiconductors wherein the desired dopant is ionized and accelerated by an electric field, penetrates the surface, and is deposited within the semiconductor material.

JESD99B, 5/07

See "infrared-emitting diode".

The density of the radiant flux incident on a surface, i.e., the radiant flux divided by the area of the irradiated surface.

JESD77-B, 2/00
IS

See "initialize input (synchronous)".

Electrical isolation of one or more elements of a single-chip semiconductor integrated circuit, achieved by surrounding the elements with an insulating barrier such as semiconductor oxide.

JESD99B, 5/07

Electrical isolation of one or more elements of a single-chip semiconductor integrated circuit, achieved by surrounding the element(s) with a region of the conductivity type that forms a junction and reverse-biasing that junction.

JESD99B, 5/07

The rms ac or dc voltage that may be applied continuously between the mounting surface and all of the terminals and also between the terminals of isolated circuits.

JESD14, 11/86

The rms ac or dc voltage used for short-time testing of the insulation between the mounting surface and all of the terminals and also between terminals of isolated circuits.

JESD14, 11/86

A latch-up test that supplies positive and negative current pulses to the pin under test.

JESD78A, 2/06

A nearly pure and ideal semiconductor in which the electron and hole densities are nearly equal under conditions of thermal equilibrium. (Ref. IEC 747‑1.)

JESD77-B, 2/00
IMC

See “intermetallic compound”.

A waveform that has a defined virtual front time and a defined virtual time to half peak value.

NOTE 1    Impulse waveshapes may be given for either voltage or current.

NOTE 2    Virtual front time is the time interval between the virtual origin and the instant when the extrapolated leading edge reaches its peak; the extrapolation is made through the 10% and 90% amplitude points for current and the 30% and 90% points for voltage.

NOTE 3    Virtual time to half-peak value is the time interval between the virtual origin and the instant when the amplitude of the trailing edge reaches 50%. This is expressed as a combined front time and time to half-peak value such as 8/20 µs or 10/1000 µs.

JESD77C, 10/09
JESD210, 12/07

The phase in the life of a device during which the mortality function is decreasing.

NOTEAs typically used with the bathtub curve, the infant mortality phase precedes the useful life of the device.

JEP143B.01, 6/08

A physical defect inherent in the process architecture, design, or layout, or created during manufacturing (wafer fabrication or assembly) that is manifested during testing or screening.

JEP143B.01, 6/08

A mark, on a device, created using applied ink, paint, or other pigment.

JESD22-B114, 3/08

The ratio of power delivered to a load with no ABD in the circuit to that delivered after the ABD is inserted.

NOTE    Insertion loss is generally expressed in decibels. It is frequency-dependent due to the inductance, capacitance, and resistance of the ABD.

JESD77C, 10/09
JESD210, 12/07

Alternative abbreviations for the word ‘‘interconnect’’.

J-STD-609, 5/07

See “integrated circuit, interface”.

A substance formed when solder comes in contact with another metal at elevated temperature.

NOTE    The IMC is composed of multiple constituents from the solder and the other metal. This material has unique mechanical and electrical properties, which are different from those of the initial solder and the other metallization.

JEP154, 1/08

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