See "gate terminal".

The point in the transfer diagram corresponding to the midstep [step] value of the step for which gain error is specified (usually full scale), and in reference to which the gain adjustment is performed.

NOTE Gain adjustment causes only a change of the slope of the transfer diagram, without changing the offset error.

A digital integrated circuit containing a fixed topology of circuit elements used to form macrocells and macro functions that are or can be interconnected to implement a logic function.

The physical area occupied by the logic gates and intercell routing excluding the pad cell area.

The number of gates in the gate core area divided by the gate core area.

NOTE Units are gates per unit area.

(2) (of a gate array): The number of available gates in the gate core area divided by the gate core area.

NOTE Units are gates per unit area.

The (control) current into the gate terminal.

The dc voltage between the gate terminal and the drain terminal.

The minimum circuitry necessary to implement a two-input NAND gate.

(2) (for ECL): One-eleventh of the minimum circuitry necessary to implement a single-bit full-adder.

A combinational logic function consisting of a number of inputs and outputs and performing one of the Boolean functions AND, OR, exclusive OR, NAND, NOR, or exclusive NOR.

NOTE For the purpose of specifying complexity, (1) buffers and inverters are counted as gates and (2) exclusive OR and exclusive NOR gates, some high-input-count gates, and memory functions are counted as multiple gates.

A control region that determines the surface charge-carrier concentration in the channel region as a function of the gate voltage.

NOTE This definition applies for the actual operating mode of the device regardless of the name of any associated terminal.

(2) (of a JFET): A control region that determines the cross-sectional area of the channel region as a function of the gate voltage.

NOTE This definition applies for the actual operating mode of the device regardless of the name of any associated terminal.

(3) (of a thyristor): A control region in which a momentary injection of controlling charge causes a regenerative turn-on action.

NOTE This definition applies for the actual operating mode of the device regardless of the name of any associated terminal.

The gate charge necessary to reach V_gs(pl) on the calculated line segment 1. (See the figure with "gate-drain charge".)

The dc voltage between the gate terminal and the source terminal.

The ratio of the number of used gates to available gates.

NOTE Gate utilization is usually expressed as a percentage.

See "gate equivalency of a function".

A representation of a function in terms of its physical implementation.

A short, undesirable transient in the analog output following a code change at the digital input.

The time integral of the electrical power of the glitch transient.

NOTE 1 Usually, the maximum specified glitch energy refers to a specified worst-case code change.

NOTE 2 Instead of a letter symbol, the abbreviation "GE" is in use.

See "ground" and "ground reference or source power voltage (pin)".

A sample used to monitor the consistency of the beam and tester setup.

A DRAM that contains special graphics features similar to those contained in an MPDRAM. (See also "synchronous graphics DRAM (SGRAM)".)

(1) The common or zero-potential pin(s) of the device under test.

NOTE 1 Ground pins are not latch-up tested.

NOTE 2 A ground pin is sometimes called VSS.

(2) A conducting connection, whether intentional or accidental, between an electrical circuit or equipment and the earth, or to some conducting body that serves in place of earth.

(3) The position or portion of an electrical circuit at zero potential with respect to the earth.

(4) A conducting body, such as the earth or the hull of a steel ship used as a return path for electric currents and as an arbitrary zero reference point.

The ground reference voltage pin for NMOS, CMOS, and TTL devices, commonly the reference pin for all other device pins. VSS is normally the system ground and the term VSS is often used interchangeably with the term GND.

See "synchronous output enable".

A transferred-electron diode intended to operate at a frequency determined by the transit time of charge packets or "domains" that are formed due to the transferred-electron effect.