(1) The loss of the ability of a component to meet the electrical or physical performance specifications that (by design or testing) it was intended to meet.

(2) A component that has failed.

(3) The lack of the ability of a component to meet the electrical or physical performance specifications that (by design or testing) it was intended to meet. (Adapted from Merriam-Webster's Collegiate Dictionary.)

The time period beginning with receipt in the failure-analysis laboratory of a failed device and associated background information and ending with submission of a failure-analysis report and closure with the customer.

The physical process that created the failure mechanism.

The physical, chemical, electrical, or other process that has led to a nonconformance.

A physical failure mechanism in which all products with the same wafer fabrication process, design rules, and processing line are treated as a homogeneous population for the purpose of statistical reliability monitoring independent of package technology, material, construction, and type.

(1) A disciplined analysis of possible failure modes on the basis of seriousness, probability of occurrence, and likelihood of detection.

(2) A systematized group of activities intended to recognize, evaluate, and prioritize the potential failure of a product or process and its effects, and to identify actions that could eliminate or reduce the chance of the potential failure occurring, listed in the order of effect on the customer.

(3) A disciplined technique to identify and prevent potential failure modes. The FMEA provides a structured analysis in order to assess the probability of occurrence of a failure as well as the effect of the failure. A fully developed FMEA is continuously maintained and updated to reflect the latest actions and changes to the design or process.

The resistance at or above which the structure is considered to have failed.

The number of failures per 10⁹ device-hours.

That part of the recovered charge that is recovered from the diode during the reverse recovery fall time.

NOTE The time intervals t_rrf and t_rrr are defined so that their sum is equal to the reverse recovery time t_rr, whereas the recovered charge Q_rr is defined for an integration time t_i. As a consequence, the sum of the partial charges Q_rrf and Q_rrr will differ from Q_rr unless t_rr equals t_i.

The number of output ports on a net.

A defect that may cause a failure in the circuit operation and/or timing.

NOTE Subclassifications of faults may not be mutually exclusive.

The ratio of detectable faults to the sum of detectable and undetectable faults.

The process of applying test vectors to a circuit or circuit model to obtain fault-coverage information.

A fast CMOS series that includes devices whose input logic levels are TTL-input-compatible and whose outputs are specified at TTL levels.

An FCT series of fast CMOS devices with reduced output swing. These devices are generally referred to as devices with TTL output swing.

The voltage that is a function of the output voltage and is used for feedback control of the regulator.

An error in analog output, due to variation in the reference voltage, that appears as an offset error and is proportional to the frequency and amplitude of the reference signal.

NOTE 1 The specification for the feedthrough error is given for the digital input for which the offset error is specified, and for a reference signal of specified frequency and amplitude.

NOTE 2 This error may also be expressed as a peak-to-peak analog value.

See "field-effect transistor".

Synonym for "registration mark".

Any failure that occurs after the completion of all the manufacturer's documented procedures and technology-conformance testing.

A gate array integrated circuit that can be electrically programmed.

Synonym for "programmable logic sequencer".

See "integrated circuit, film".

A layer of solid material formed by any deposition process upon the substrate or upon other films deposited on the substrate.

The technology with which electronic circuits or elements are formed by applying a liquid, solid, or paste coating through a screen or mask in a selective pattern onto a supporting material.

NOTE This technology also includes films deposited by any other means when the films so formed are five micrometers or greater in thickness.

A film produced by a printing process, serigraphy, or other related techniques.

A fine feather-edge protrusion occurring at an edge.

A process of thick-film formation whereby the screened film is subjected to a precisely controlled high-temperature condition that oxidizes and vaporizes organic binders and modifies the film microstructure to achieve desired properties, including adherence to the substrate.

A memory from which data can be read only in the same order as entered, although not necessarily at the same rate.

The external dimensions and associated tolerances of the product, as specified by the supplier and/or customer.

A metallization pattern that interconnects circuit elements and is defined by a single, predesigned mask.

An information bit that indicates the occurrence of special conditions such as overflow, carry, or interrupt.

An EEPROM in which clearing can be performed only on blocks or on the entire array.

NOTE There are no restrictions on the block architecture in the definition of FEEPROM. The blocks within a device may be of various capacities ranging from a single address to the entire memory array.

A package whose leads project parallel to, and are designed primarily to be attached parallel to, the seating plane.

NOTE The term "flatpack" has been replaced by "quad flatpack" (for terminals on three or four sides) and "small-outline package" (for terminals on one or two sides).

A netlist in which all logic elements are connected at the lowest hierarchical level.

An unpackaged die whose interconnection to a substrate is formed through solder joints.

A signal line that is not actively forced to a defined high or low level.

NOTE In a high-impedance state, the charge (or lack of charge) is trapped at the node with no path to supply or ground voltages.

The allowable time period between removal of moisture-sensitive devices from a moisture barrier bag, dry storage, or dry bake and the solder reflow process.

Creating a chart that details a chronological sequence of process steps, which provides an opportunity to identify areas for improvement in efficiency and effectivity.

The number of radiant-energy particles emitted from or incident on a surface in a given period of time, divided by the area of the surface.

NOTE 1 The equation "fluence = N/A" applies, where N and A represent the quantities number of particles and area. Fluence can also be calculated by integrating the flux density over the given period of time, e.g., as in a run.

NOTE 2 The unit symbol (e.g., cm^‑²) does not identify particle type. The particle name may be placed before the term, e.g., "neutron fluence", or in the spelled-out unit name, e.g., "neutrons per square centimeter".

NOTE 3 Fluence of particle radiation incident on a surface is maximized when the surface is perpendicular to the direction of the incident particle flow.

The luminous flux at a surface divided by the area of the surface. (See also "illuminance" and "luminous exitance".)

(2) (radiant): The radiant flux at a surface divided by the area of the surface. (See also "irradiance" and "radiant exitance".)

(3) flux density (of particle radiation): The time rate of flow of radiant-energy particles emitted from or incident on a surface, divided by the area of that surface.

NOTE 1 The equation "flux density = N/A∙t" applies, where N, A, and t represent the quantities number of particles, area, and time.

NOTE 2 The unit symbol (e.g., cm^‑2·s^‑1) does not identify particle type. The particle name may be placed before the term, e.g., "neutron flux density", or in the spelled-out unit name, e.g., "neutrons per square centimeter second".

NOTE 3 Flux density is maximized when the surface is perpendicular to the direction of the emitted or incident particle flow.

The distance in water at which the spot size of the transducer is at a minimum.

A relatively thin layer of solid material that can be handled independently of a substrate.

The pattern of package leads that is used to define the land patterns on a mating printed circuit board.

NOTE The footprint may include features necessary for mechanical mounting of the package.

The visual appearance including shape, color, marking, and surface finish of the product, as specified by the supplier and/or customer.

The bias that tends to produce forward current.

A three-terminal thyristor surge protective device that switches only for negative main terminal-2 (cathode) voltage and conducts large currents at positive main terminal-2 (cathode) voltages comparable in magnitude to the on‑state voltage.

NOTE 1 In conventional thyristor terminology, this device would be called a reverse-conducting triode thyristor.

NOTE 2 Application of an appropriate fixed gate voltage allows switching to take place at voltages well below the intrinsic breakover value.

The direction of a (positive) forward current.

(2) (in an avalanche-junction transient voltage suppressor): The direction of current that results when the p‑type semiconductor region connected to one terminal is at a positive potential relative to the n‑type region connected to the other terminal.

NOTE Any capacitance-reduction diodes that may be included shall be ignored in the determination of forward direction.

The direct current into the gate terminal of an insulated gate field-effect transistor with a forward gate-source voltage applied and the drain terminal short-circuited to source terminal.

The part of an alternating-voltage cycle during which forward voltage appears across the rectifier circuit element.

A rectifier diode whose cathode is connected to the mounting stud or heat sink.

The time interval between the instant when the forward voltage rises through a specified first value, usually 10% of its final value, and the instant when it falls from its peak value, V_FRM, to a specified low second value, V_FR, upon the application of a step current following a zero-voltage or a specified reverse-voltage condition.

See "field-programmable gate array".

See "field-programmable logic sequencer".

Synonym for "ambient temperature".

The condition of a phase-locked loop (PLL) device where the frequency of the feedback input is equal to the averaged reference input frequency within a designated tolerance.

See "flow through".

Synonym for "duplex transmission".

A term used to refer a characteristic to the negative end of the transfer diagram, that is, to the step whose nominal midstep [step] value has the most negative value.

NOTE 1 The subscript for the letter symbol of a characteristic at negative full scale is "FS-" (e.g., V_FS-, I_FS-).

NOTE 2 In place of a letter symbol, the abbreviation "FS-" is commonly used.

A term used to refer a characteristic to the positive end of the transfer diagram, that is, to the step whose nominal midstep [step] value has the most positive value.

NOTE 1 The subscript for the letter symbol of a characteristic at positive full scale is "FS+" (e.g., V_FS+, I_FS+).

NOTE 2 In place of a letter symbol, the abbreviation "FS+" is commonly used.

The total range of analog values that correspond to the ideal straight line.

NOTE 1 The qualifying adjective "practical" may nearly always be deleted from this term, provided that the term "nominal full-scale range" is not also shortened by deleting "nominal". This permits use of the shorter letter symbols or abbreviations. (See note 2.)

NOTE 2 In place of the letter symbols "V_FSR" and "I_FSR", the abbreviation "FSR" is commonly used; in place of the letter symbols "V_FSRpr" and "I_FSRpr", the abbreviation "FSR(pr)" is commonly used.

NOTE 3 The (practical) full-scale range has only a nominal value because it is defined by the end points of the ideal straight line.

EXAMPLE Using a straight binary n-bit code format, it follows that

FSR = (2ⁿ - 1) x (nominal value of step width), for an analog-to-digital converter, and

FSR = (2ⁿ - 1) x (nominal value of step height), for a digital-to-analog converter.

A circuit that changes single-phase alternating current into pulsating unidirectional current utilizing both halves of each cycle.

The electrical, mechanical, and thermal performance characteristics of the product, as specified by the supplier and/or customer.

The number of gates used divided by the entire chip area.

NOTE Units are gates used per unit area.

A fault that causes improper logical operation of a circuit.

An identifiable volume whose boundaries depend on operating conditions.

EXAMPLES space-charge region, channel region.

The process of verifying the specified functions of a device without regard to timing.

See "flash write with mask".

Pertaining to the portion of the semiconductor processing line that creates the metal layer (e.g., the under-bump-metal or redistribution layer) and associated interconnect structures forming the connection between on-chip and off-chip wiring.

The expected time a product will function or be needed in the field determined.

The portion of the voltage-current characteristic of a unidirectional ABD forward-biased p‑n junction that exhibits a low small-signal resistance to the passage of current.

Pertaining to the portion of the semiconductor processing line that creates active devices and ends with the gate-oxide conductors.