See "refresh (F)".
See "refresh (F)".
(1) The loss of the ability of a component to meet the electrical or physical performance specifications that (by design or testing) it was intended to meet.
(2) A component that has failed.
(3) The lack of the ability of a component to meet the electrical or physical performance specifications that (by design or testing) it was intended to meet. (Adapted from Merriam-Webster's Collegiate Dictionary.)
(1) A methodical process of testing, dissecting, and inspecting a semiconductor device that is suspected of malfunctioning with the goals of locating the failure site and determining the cause of failure.
(2) Investigation to determine the failure mechanism of an electrical or visual/mechanical nonconforming component.
The time period beginning with receipt in the failure-analysis laboratory of a failed device and associated background information and ending with submission of a failure-analysis report and closure with the customer.
A person, employed by either the manufacturer of the failed device or an independent laboratory, skilled in failure analysis of semiconductor devices.
The physical process that created the failure mechanism.
The number of failures detected per unit beam fluence.
The physical, chemical, electrical, or other process that has led to a nonconformance.
A physical failure mechanism in which all products with the same assembly technology, including assembly material, assembly construction, and package type, and built on the same assembly line are treated as a homogeneous population for the purpose of statistical reliability monitoring independent of fabrication process and line.
A physical failure mechanism in which all products with the same wafer fabrication process, design rules, and processing line are treated as a homogeneous population for the purpose of statistical reliability monitoring independent of package technology, material, construction, and type.
The way in which a failure mechanism manifests itself in a failing component.
(2) (in a BGA ball shear test): The type or location of failure observed after the solder ball is sheared.
(1) A disciplined analysis of possible failure modes on the basis of seriousness, probability of occurrence, and likelihood of detection.
(2) A systematized group of activities intended to recognize, evaluate, and prioritize the potential failure of a product or process and its effects, and to identify actions that could eliminate or reduce the chance of the potential failure occurring, listed in the order of effect on the customer.
(3) A disciplined technique to identify and prevent potential failure modes. The FMEA provides a structured analysis in order to assess the probability of occurrence of a failure as well as the effect of the failure. A fully developed FMEA is continuously maintained and updated to reflect the latest actions and changes to the design or process.
The fraction of a population that fails within a specified interval, divided by that interval.
NOTE 1 Standard methods of reporting failure rates of semiconductor devices include 1) percent failed per 1000 hours and 2) FITs.
NOTE 2 The interval may be expressed in operating hours, storage hours, operating cycles, or other units of interval measurement.
NOTE 3 Typically, the term "failure rate" means the instantaneous failure (hazard) rate.
NOTE 4 The statistical upper limit estimate of the failure rate is usually calculated using the χ² (chi-squared) function.
The resistance at or above which the structure is considered to have failed.
The subset of the sample that fails the defined test criterion during the stress time.
The number of failures per 109 device-hours.
The time interval between one reference point on a waveform and a second reference point of smaller magnitude on the same waveform.
NOTE The first and second reference points are usually 90% and 10%, respectively, of the steady‑state amplitude of the waveform existing before the transition, measured with respect to the steady‑state amplitude existing after the transition.
(2) (of an analog integrated circuit): For a step-function change of the input signal level, the time interval between the end of the delay time (normally 90%) and that instant at which the magnitude of the output signal first passes through a specified value (normally 10%) close to its final value. (Ref. IEC 747‑3.)
(3) (of a digital integrated circuit): Synonym for "transition time, high-to-low level".
(4) (of a transistor): (A) The time interval during which the amplitude of the trailing edge of a pulse decreases from 90% to 10% of its maximum amplitude.
(B) Synonym for "current fall time, tfi".
That part of the recovered charge that is recovered from the diode during the reverse recovery fall time.
NOTE The time intervals trrf and trrr are defined so that their sum is equal to the reverse recovery time trr, whereas the recovered charge Qrr is defined for an integration time ti. As a consequence, the sum of the partial charges Qrrf and Qrrr will differ from Qrr unless trr equals ti.
Synonym for "inadvertent-write protection".
The number of output ports on a net.
The number of input ports on a net.
A defect that may cause a failure in the circuit operation and/or timing.
NOTE Subclassifications of faults may not be mutually exclusive.
The percentage of possible faults detected by a set of test vectors.
The ratio of detectable faults to the sum of detectable and undetectable faults.
The process of determining the test-pattern fault coverage of a circuit.
The process of applying test vectors to a circuit or circuit model to obtain fault-coverage information.
A design approach intended to enhance the ability of a circuit to remain operational after the occurrence of a fault.
NOTE Fault-tolerant design techniques may impact fault detection.
A fast CMOS series that includes devices whose input logic levels are TTL-input-compatible and whose outputs are specified at TTL levels.
An FCT series of fast CMOS devices with a complementary output stage. These are generally referred to as devices with CMOS output swing.
An FCT series of fast CMOS devices with reduced output swing. These devices are generally referred to as devices with TTL output swing.
A physical portion of a part, such as a surface, hole, or slot.
The voltage that is a function of the output voltage and is used for feedback control of the regulator.
The value of the capacitance for a specified value of resistance in an equivalent circuit for the calculation of the feedthrough error.
NOTE The equivalent circuit consists of a high-pass R-C filter between the reference input and analog output.
An error in analog output, due to variation in the reference voltage, that appears as an offset error and is proportional to the frequency and amplitude of the reference signal.
NOTE 1 The specification for the feedthrough error is given for the digital input for which the offset error is specified, and for a reference signal of specified frequency and amplitude.
NOTE 2 This error may also be expressed as a peak-to-peak analog value.
See "flash EEPROM".
See "field-effect transistor".
See "integrated circuit, film".
Synonym for "registration mark".
A transistor in which the conduction is due entirely to the flow of majority carriers through a conduction channel controlled by an electric field arising from a voltage applied between the gate and the source.
NOTE For graphical symbols, see JESD77-B, 4.3.1.
Any failure that occurs after the completion of all the manufacturer's documented procedures and technology-conformance testing.
A charging method using electrostatic induction.
A gate array integrated circuit that can be electrically programmed.
Synonym for "programmable logic array".
Synonym for "programmable logic sequencer".
A read-only memory that, after being manufactured, can have the data content of each memory cell altered. (Ref. IEC 748‑2.)
See "integrated circuit, film".
Synonym for "integrated circuit, film".
A layer of solid material formed by any deposition process upon the substrate or upon other films deposited on the substrate.
A film obtained through chemical and/or electrochemical deposition.
The technology with which electronic circuits or elements are formed by applying a liquid, solid, or paste coating through a screen or mask in a selective pattern onto a supporting material.
NOTE This technology also includes films deposited by any other means when the films so formed are five micrometers or greater in thickness.
The technology with which electronic circuits or elements are formed by vapor deposition, vacuum deposition, or sputtering of films onto a supporting material.
NOTE This technology also includes similar techniques when the films so formed are less than five micrometers in thickness.
A film produced by a printing process, serigraphy, or other related techniques.
A film produced by an accretion process such as vapor-phase deposition or sputtering.
A fine feather-edge protrusion occurring at an edge.
A special case of signature analysis where the signature occurs in a particular finite population of devices.
A process of thick-film formation whereby the screened film is subjected to a precisely controlled high-temperature condition that oxidizes and vaporizes organic binders and modifies the film microstructure to achieve desired properties, including adherence to the substrate.
The program instructions stored in a read-only memory.
NOTE Computer programs stored on disks, including hard drives and CD-ROMs, are customarily referred to as software.
A memory from which data can be read only in the same order as entered, although not necessarily at the same rate.
See "cause and effect diagram".
The external dimensions and associated tolerances of the product, as specified by the supplier and/or customer.
See "failures in time".
A metallization pattern that interconnects circuit elements and is defined by a single, predesigned mask.
A read-only memory in which the data content of each cell is determined during manufacture and is thereafter unalterable. (Ref. IEC 748‑2.)
An information bit that indicates the occurrence of special conditions such as overflow, carry, or interrupt.
A package having a flange-mounted heat sink that is an integral part of the package and extends beyond the package body to provide mechanical mounting to a packaging interconnect structure or cold plate.
NOTE The terminals may exit from, or be attached to, any surface of the package.
An EEPROM in which clearing can be performed only on blocks or on the entire array.
NOTE There are no restrictions on the block architecture in the definition of FEEPROM. The blocks within a device may be of various capacities ranging from a single address to the entire memory array.
A write cycle in which the contents of an entire row of the memory array can be selectively set to the stated value. The "mask" value determines which bit planes are to be altered while the "color register" contains the data value to be written. The color register is loaded in a previous load-color-register cycle with a persistent value. The mask value is supplied during the cycle on the DQ(n) terminals. A new mask value must be supplied for each cycle performed. A high mask bit normally enables the write function for that bit. A low mask bit leaves the data unaltered.
A package whose leads project parallel to, and are designed primarily to be attached parallel to, the seating plane.
NOTE The term "flatpack" has been replaced by "quad flatpack" (for terminals on three or four sides) and "small-outline package" (for terminals on one or two sides).
A geometric description in which all geometries are contained at the lowest hierarchical level.
A netlist in which all logic elements are connected at the lowest hierarchical level.
Propagation time of the signal on a transmission line.
An unpackaged die whose interconnection to a substrate is formed through solder joints.
A gate electrode that has no ohmic connection and is isolated from the semiconductor by an insulating layer or junction.
NOTE 1 The potential on the floating gate depends on the quantity of electrical charge stored in a potential well under the surface.
NOTE 2 Floating gates are typically used in signal detection or regeneration circuits.
A signal line that is not actively forced to a defined high or low level.
NOTE In a high-impedance state, the charge (or lack of charge) is trapped at the node with no path to supply or ground voltages.
A high-conductivity doped region without ohmic connection into or from which charge packets are transferred by overlapping or adjacent transfer gates.
NOTE A floating region can be used as the sense node for the charge signal in detection or regenerating circuits.
The allowable time period between removal of moisture-sensitive devices from a moisture barrier bag, dry storage, or dry bake and the solder reflow process.
The process of defining the physical placement of circuit elements.
Creating a chart that details a chronological sequence of process steps, which provides an opportunity to identify areas for improvement in efficiency and effectivity.
A control input that, when true, places the RAM register into the flow-through mode and, when false, places the RAM register into the register mode.
The number of radiant-energy particles emitted from or incident on a surface in a given period of time, divided by the area of the surface.
NOTE 1 The equation "fluence = N/A" applies, where N and A represent the quantities number of particles and area. Fluence can also be calculated by integrating the flux density over the given period of time, e.g., as in a run.
NOTE 2 The unit symbol (e.g., cm‑²) does not identify particle type. The particle name may be placed before the term, e.g., "neutron fluence", or in the spelled-out unit name, e.g., "neutrons per square centimeter".
NOTE 3 Fluence of particle radiation incident on a surface is maximized when the surface is perpendicular to the direction of the incident particle flow.
The time rate of flow of luminous energy.
(2) (radiant): The time rate of flow of radiant energy.
(3) (of particle radiation): Used as a synonym for "flux density" only in JESD57 and JESD89A.
The luminous flux at a surface divided by the area of the surface. (See also "illuminance" and "luminous exitance".)
(2) (radiant): The radiant flux at a surface divided by the area of the surface. (See also "irradiance" and "radiant exitance".)
(3) flux density (of particle radiation): The time rate of flow of radiant-energy particles emitted from or incident on a surface, divided by the area of that surface.
NOTE 1 The equation "flux density = N/A∙t" applies, where N, A, and t represent the quantities number of particles, area, and time.
NOTE 2 The unit symbol (e.g., cm‑2·s‑1) does not identify particle type. The particle name may be placed before the term, e.g., "neutron flux density", or in the spelled-out unit name, e.g., "neutrons per square centimeter second".
NOTE 3 Flux density is maximized when the surface is perpendicular to the direction of the emitted or incident particle flow.
See "failure mode and effect analysis".
The distance in water at which the spot size of the transducer is at a minimum.
The X-Y plane at a depth (Z) in which the amplitude of the acoustic signal is maximized.
A relatively thin layer of solid material that can be handled independently of a substrate.
A type of overload protection for voltage regulators wherein, under overload conditions, the load current is reduced to some low level relative to a limiting load current.
The pattern of package leads that is used to define the land patterns on a mating printed circuit board.
NOTE The footprint may include features necessary for mechanical mounting of the package.
Any adhering residue that is not of the piece part composition under inspection and cannot be removed by a dry-gas blow-off of 50 pounds per square inch (345 kilopascals) and/or by a suitable brush that will not scratch or damage the surface of the part.
The visual appearance including shape, color, marking, and surface finish of the product, as specified by the supplier and/or customer.
The ratio of the root-mean-square value of the wave to the average value.
The bias that tends to produce forward current.
A two-terminal internally triggered thyristor surge protective device that switches only for negative terminal-2 (cathode) voltage and conducts large currents at positive terminal-2 (cathode) voltages comparable in magnitude to the on‑state voltage.
NOTE 1 In conventional thyristor terminology, this device would be called a reverse-conducting diode thyristor.
NOTE 2 When terminal 2 (cathode) is positive, the device characteristics are similar to those of a forward-biased diode.
NOTE 3 When terminal 2 (cathode) is negative, the device characteristics are similar to those of a breakover-triggered SCR.
A three-terminal thyristor surge protective device that switches only for negative main terminal-2 (cathode) voltage and conducts large currents at positive main terminal-2 (cathode) voltages comparable in magnitude to the on‑state voltage.
NOTE 1 In conventional thyristor terminology, this device would be called a reverse-conducting triode thyristor.
NOTE 2 Application of an appropriate fixed gate voltage allows switching to take place at voltages well below the intrinsic breakover value.
The current flowing from the p‑type region to the n‑type region.
(2) (in a semiconductor diode): The current flowing from the external circuit into the anode terminal.
The direction of a (positive) forward current.
(2) (in an avalanche-junction transient voltage suppressor): The direction of current that results when the p‑type semiconductor region connected to one terminal is at a positive potential relative to the n‑type region connected to the other terminal.
NOTE Any capacitance-reduction diodes that may be included shall be ignored in the determination of forward direction.
The direct current into the gate terminal with a forward gate-source voltage applied.
The direct current into the gate terminal of an insulated gate field-effect transistor with a forward gate-source voltage applied and the drain terminal short-circuited to source terminal.
The mode in which the drain-to-source polarity during test is the same as that during the application of stress.
The part of an alternating-voltage cycle during which forward voltage appears across the rectifier circuit element.
A microwave diode in which the anode is connected to the base (i.e., the larger-diameter terminal) of the package.
A rectifier diode whose cathode is connected to the mounting stud or heat sink.
The power dissipation resulting from forward current.
The time interval between the instant when the forward voltage rises through a specified first value, usually 10% of its final value, and the instant when it falls from its peak value, VFRM, to a specified low second value, VFR, upon the application of a step current following a zero-voltage or a specified reverse-voltage condition.
The voltage between the p‑type region and the n‑type region when the p‑type region is at a positive voltage relative to the n‑type region.
(2) (across a semiconductor diode): A positive anode-cathode voltage.
See "field-programmable gate array".
See "field-programmable logic array".
See "field-programmable logic sequencer".
The unknown nonconforming proportion of the total population of components. Estimates of fraction nonconforming are derived from samples.
Synonym for "ambient temperature".
The state of a component that is not attached to the next level of assembly packaging.
The condition of a phase-locked loop (PLL) device where the frequency of the feedback input is equal to the averaged reference input frequency within a designated tolerance.
The nth fringe in a sequence of interference fringes.
See "flow through".
Two half-bridge outputs with the load connected between them.
NOTE The outputs are normally operated in a complementary fashion; i.e., as one output goes high, the other goes low. If one or both outputs are three-state outputs or if the operation is not complementary, the load current can be turned off.
Synonym for "duplex transmission".
The difference between the actual midstep [step] value and the nominal midstep [step] value at specified full scale.
NOTE Normally, this error specification is applied to converters that have no arrangement for an external adjustment of offset error and gain error.
A term used to refer a characteristic to the negative end of the transfer diagram, that is, to the step whose nominal midstep [step] value has the most negative value.
NOTE 1 The subscript for the letter symbol of a characteristic at negative full scale is "FS-" (e.g., VFS-, IFS-).
NOTE 2 In place of a letter symbol, the abbreviation "FS-" is commonly used.
A term used to refer a characteristic to that step within the transfer diagram whose nominal midstep [step] value has the highest absolute value.
NOTE 1 The subscript for the letter symbol of a characteristic at full scale is "FS".
NOTE 2 In place of a letter symbol, the abbreviation "FS" is commonly used.
A term used to refer a characteristic to the positive end of the transfer diagram, that is, to the step whose nominal midstep [step] value has the most positive value.
NOTE 1 The subscript for the letter symbol of a characteristic at positive full scale is "FS+" (e.g., VFS+, IFS+).
NOTE 2 In place of a letter symbol, the abbreviation "FS+" is commonly used.
The total range in analog values that can be coded with uniform accuracy by the total number of steps, with this number rounded up to the next higher power of 2.
NOTE In place of the letter symbols "VFSRnom" and "IFSRnom", the abbreviation "FSR(nom)" is commonly used.
EXAMPLE Using a straight binary n-bit code format, it follows that
FSR(nom) = 2n x (nominal value of step width), for an analog-to-digital converter, and
FSR(nom) = 2n x (nominal value of step height), for a digital-to-analog converter.
The total range of analog values that correspond to the ideal straight line.
NOTE 1 The qualifying adjective "practical" may nearly always be deleted from this term, provided that the term "nominal full-scale range" is not also shortened by deleting "nominal". This permits use of the shorter letter symbols or abbreviations. (See note 2.)
NOTE 2 In place of the letter symbols "VFSR" and "IFSR", the abbreviation "FSR" is commonly used; in place of the letter symbols "VFSRpr" and "IFSRpr", the abbreviation "FSR(pr)" is commonly used.
NOTE 3 The (practical) full-scale range has only a nominal value because it is defined by the end points of the ideal straight line.
EXAMPLE Using a straight binary n-bit code format, it follows that
FSR = (2n - 1) x (nominal value of step width), for an analog-to-digital converter, and
FSR = (2n - 1) x (nominal value of step height), for a digital-to-analog converter.
An analog value derived from the nominal full‑scale range:
- for a unipolar converter, VFSnom = VFSRnom; (IFSnom = IFSRnom)
- for a bipolar converter, VFSnom = ½ VFSRnom; (IFSnom = ½ IFSRnom).
NOTE 1 In some data sheets, this analog value is used as a reference value for adjustment procedures or as a rounded value for the full-scale range.
NOTE 2 In place of the letter symbols "VFSnom" and "IFSnom", the abbreviation "FS(nom)" is commonly used.
A circuit that changes single-phase alternating current into pulsating unidirectional current utilizing both halves of each cycle.
Synonym for "charge-handling capacity".
The electrical, mechanical, and thermal performance characteristics of the product, as specified by the supplier and/or customer.
A part of a circuit having a defined function that can be designated by a single symbol in a schematic representation.
The number of gates used divided by the entire chip area.
NOTE Units are gates used per unit area.
Failure of a device to deliver correct output data or signals during operation (e.g., stuck-high or stuck-low output, open input or output, logic error, etc.).
A fault that causes improper logical operation of a circuit.
The functional models of a set of macros.
An identifiable volume whose boundaries depend on operating conditions.
EXAMPLES space-charge region, channel region.
The process of exercising a particular netlist and functional models by applying input stimuli to observe the functional responses without regard to timing.
The process of verifying the specified functions of a device without regard to timing.
A tabulation relating all output digital levels to all necessary or possible input digital levels for sufficient successive time intervals (tn, tn+1) to completely characterize the static and dynamic functions of the digital integrated circuit.
NOTE 1 Digital levels may be expressed in electrical values directly or by predefined symbolic equivalents.
NOTE 2 Contrast with "truth table".
See "flash write with mask".
The characteristics of failure for a given physical failure mechanism, including (where applicable) acceleration factor, derating curve, activation energy, median life, standard deviation, characteristic life, instantaneous failure rate, etc.
Pertaining to the portion of the semiconductor processing line that creates the metal layer (e.g., the under-bump-metal or redistribution layer) and associated interconnect structures forming the connection between on-chip and off-chip wiring.
The portion of the semiconductor processing line that creates the metal layer (e.g., the under-bump-metal or redistribution layer) and associated interconnect structures forming the connection between on-chip and off-chip wiring.
The expected time a product will function or be needed in the field determined.
A controlled-temperature chamber capable of maintaining specified subfreezing temperatures over the entire working area.
The portion of the voltage-current characteristic of a unidirectional ABD forward-biased p‑n junction that exhibits a low small-signal resistance to the passage of current.
The state of a component that is not attached to the next level of assembly packaging.
Pertaining to the portion of the semiconductor processing line that creates active devices and ends with the gate-oxide conductors.
The portion of the semiconductor processing line that creates active devices and ends with the gate-oxide conductors.
Contact Julie Carlson, 703-624-9230