The customer initial-use period, typically the first 2,500 to 10,000 hours of operation.

The failure rate that may occur during the period of initial use by the customer.

The specified early life period as defined by the user or the supplier.

Error detection and correction.

See "redundancy (in a memory)".

The linear energy transfer (LET) modified to account for the change in total energy transferred from an incident ion as it traverses a sensitive volume when the path of the ion is not normal to the surface of that volume.

NOTE 1 The cosine dependence may be applicable for this modification. Caution must be utilized; see annex B of JESD57.

LET(θ ) = LET(0°) / cos θ

where θ is the angle of incidence of the ion (i.e., the angle between the ion path and the normal at the point of incidence).

NOTE 2 Many modern devices do not follow the above equation, so the experimenter may have to determine the LET(θ ) from the geometry of a particular device.

NOTE 3 The equation in note 1 is valid only when the depth of the sensitive volume is less than the other two dimensions in the RPP model.

An electrically conducting element that is intended to function as a pathway between other elements, including terminals, and whose primary purpose is to conduct electric current in a confined manner.

NOTE The connection may consist of a separate conductive entity such as a wire or metallic film or be an integral part of the body.

The time interval required for an electrical signal to traverse the conductor from end to end.

An electrical characteristic value, such as inductance or capacitance, that, when used in a simulation process, will produce signal transfer characteristics reproducing those measured.

(1) An electrical and mechanical contact to a region of a semiconductor device.

(2) An element that performs one or more functions of emitting or collecting electrons or holes, or of controlling their movements by an electric field.

A sudden transfer of electrostatic charge between bodies or surfaces at different electrostatic potentials.

The lowest level level of electrostatic discharge (ESD) that produces changes in device characteristics such that the device fails to meet its specified parameters.

A barrier or enclosure that limits the penetration of an electrostatic field so that its effects do not reach the stored or contained devices and produce damage.

The physical realization of an element incorporating more than one primary electrical characteristic (resistance, capacitance, inductance, gain, etc.) dispersed along the length of the element.

See "early-life-failure rate".

A gate array masterslice in which some of the array circuit elements are replaced by one or more cell-based functions.

The ratio of the radiant energy emitted by a surface to that emitted by a blackbody at the same temperature.

The dc current into the emitter terminal when it is biased in the reverse direction with respect to the base terminal and the collector terminal is open-circuited. (Ref. IEEE Std 255.)

The overall combination of emitter transition region, emitter region, emitter terminal, and the interface between them.

NOTE This term should be used in this manner only when no confusion is likely to occur.

A supply region that delivers principal-current charge carriers into a controlling base region through an associated emitting junction.

NOTE This definition applies for the actual operating mode of the device regardless of the name of any associated terminal. In the normal operating mode, this functional region is located in the emitter region; in the inverse operating mode, it is located in the collector region.

(1) A region from which charge carriers that will become minority carriers in the base are injected into the base. (Ref. 60 IRE 28.S1.)

(2) The physical region that is designed by the manufacturer to contain the supply region in the normal operating mode and, in a simple discrete transistor, is externally accessible by the designated emitter terminal.

A semiconductor junction in an operating condition in which the net flow of charge carriers of each type across the junction is in the direction from the region where they are majority carriers to the region where they are minority carriers, i.e., in the direction opposite to the force resulting from the internal electric field.

The time interval between the transition of the enabling signal and the instant when the supply current has increased from its standby value to its active value.

NOTE This interval is defined with respect to specified reference points on the chip-enable and supply-current waveforms.

The propagation time between specified reference points on the input and output voltage waveforms with the output changing from a high-impedance (off) state to either of the defined active levels (high or low).

The propagation time between specified reference points on the input and output voltage waveforms with the output changing from a high-impedance (off) state to the defined low level.

NOTE 1 See note 1 to "disable time from the high level …".

NOTE 2 Because L-type open-circuit outputs are used with pull-up components that cause the outputs to go high when the outputs are turned off, the term "high-to-low-level propagation time" and the symbol t_PHL are frequently used with these outputs for this parameter.

The transition time between specified reference points on the output voltage waveform with the output changing from a high-impedance (off) state to the defined low level.

NOTE 1 See note 1 to "disable time from the high level …".

NOTE 2 Because L-type open-circuit outputs are used with pull-up components that cause the outputs to go high when the outputs are turned off, the term "high-to-low-level transition time" and the symbol t_THL are frequently used with these outputs for this parameter.

A parameter that characterizes the product (e.g., piece parts, subassemblies, and/or assemblies) at the finished product stage.

The ability of a reprogrammable read-only memory to withstand data rewrites and still comply with its specifications.

The operation of a field-effect transistor such that changing the gate-source voltage from zero to a finite value increases the magnitude of the drain current. (Ref. IEC 747‑8.)

A field-effect transistor having substantially zero channel conductance for zero gate-source voltage; the channel conductance may be increased by the application of a gate-source voltage of appropriate polarity. (Ref. IEC 747‑8.)

A temperature cycle in an application resulting from environmental temperature changes.

A monocrystalline layer formed by epitaxy, which is normally of a different conductivity type or resistivity from the substrate material.

Deposition of a monocrystalline layer of material on a substrate material such that the layer thus formed has the same crystal orientation as the substrate.

NOTE Examples are silicon on silicon and silicon on sapphire.

The degree of wetting in which the forces of wetting are in equilibrium with the forces of gravity.

NOTE Visible indication of this is when the wetting balance curve flattens out and approaches zero slope.

The free-fall drop height from which an object at rest must fall, in vacuum under standard gravity, to attain a velocity equal to the velocity change stated in the test specification.

To remove information from a memory. (Ref. IEC 748‑2.)

NOTE In the field of electrically erasable programmable read-only memories, "erase" conventionally means the removal of electrons from the floating gate of the memory cell.

The corruption of data in one location caused by the erasing of data at another location.

(1) The band centered around the target time to failure, t_FT, within which the SWEAT algorithm will not permit the feedback control loop to adjust the forcing current, and whose boundaries (t_FT + B_E and t_FT - B_E) constitute the limits for the estimated time to failure, t_FE, where B_E is half the width of the error band.

(2) The criterion for convergence to the target test temperature. Convergence is defined as the point at which the difference between an extreme value of the calculated instantaneous temperature curve and the target test temperature (a) first reaches a value smaller than ε(T), where ε(T) is half the width of the error band, for a critically damped or overdamped system, or (b) remains less than ε(T) after a specified number of cycles, for an underdamped system.

The point, electrodes, bus bar, metal strips, or other system of conductors that form a path from a statically charged person or object to ground.

A work position with materials and equipment that limit electrostatic voltages or dissipate electrostatic charge.

A table top or other work surface that has a resistance to ground of less than 1 × 10⁹ ohms.

The lumped parameter device resistance in series with the device gate-source capacitance.

A solution used for etching.

A process in which material is removed by a reaction with chemically active radicals created by an ion bombardment in a glow discharge.

NOTE A mask is usually used in order to remove only selected areas.

See "exponentially weighted moving average (chart)".

A computer-based form of artificial intelligence that provides decision-making capabilities within a system, based on a preprogrammed decision tree founded on knowledge of the process parameters and their interaction.

The threshold voltage extrapolated from measurement of the maximum slope g_m(max) of the I_D-V_GS curve, as described in ASTM F617‑86. V_T(ext) can be calculated using

V_T(ext) = V_GS(gm(max)) - I_D(gm(max)) /g_m(max)

where

V_GS(gm(max)) is the gate voltage at the point of the maximum slope of the I_D-V_GS curve;
I_D(gm(max)) is the drain current at the point of the maximum slope of the I_D-V_GS curve;
g_m(max) is the maximum slope of the I_D-V_GS curve in the linear region.

A semiconductor with charge-carrier concentration dependent upon impurities or other imperfections. (Ref. IEC 747‑1.)