See "drain terminal".
See "drain terminal".
See "digital-to-analog [D/A] converter".
The condition attained when the electrical parameter under consideration approaches a value that cannot be altered by further irradiation shielding.
The output current under dark conditions.
A variation of the dark current that exceeds some specified level above the average value.
A compound semiconductor device consisting of two transistors in which the collectors are connected together and the emitter of the first transistor is connected to the base of the second transistor.
NOTE 1 The two transistors connected in this manner may be regarded as a compound transistor with three terminals.
NOTE 2 The circuit may include a biasing network.
NOTE 3 The presence of a terminal to provide direct access to the base of the second transistor is optional.
Graphic symbols (ref. IEEE Std 315):
NOTE In the graphic symbols, the envelope is optional if no element is shown connected to the envelope.
A method, used to determine whether the write operation in a memory is complete, wherein the memory is put into the read mode after initiating the write mode; if writing is complete, the outputs take on the addressed stored data, or if writing is not complete, the specified output(s) take on the complement of the last bit(s) written.
NOTE If writing is not complete: (a) in older devices, normally all outputs take on the complement of the last bits written; (b) in more modern byte-wide memories, only the most significant output takes on the complement of the last bit written; (c) in word-wide memories, the most significant output of the least significant byte, the most significant output of the entire word, or both of these outputs take on the complement of the last bit written.
A bus used to communicate data internally and externally to and from processing units, storage devices, or peripheral devices. (Adapted from ANSI X3.172.)
An event in which at least one bit of data is caused to change.
NOTE This event may be used as a unit of endurance for erasable programmable read-only memories.
A cycle in which each bit changes to its opposite state and back to its original state.
NOTE 1 These changes may occur for all bits in parallel or in series, e.g., by page, block, word, byte, or bit.
NOTE 2 This cycle may be used as a unit of endurance for erasable programmable read-only memories.
Those inputs whose states represent the data that is to be written into the selected address on a write cycle of an alterable memory device. When the numbering of the data inputs is significant for device operation, the data inputs are numbered beginning with 0. In devices where data bit groupings have independent control, an additional suffix "x" is applied. "x" takes the values of a, b, c, etc.
The pins that serve as data output(s) when in the read mode and as data input(s) when in the write mode. When the device is not selected or enabled, the output(s) are in a floating state. On devices having both serial and parallel access ports, these pins provide access to the parallel RAM port data channels. The suffix (n) is a numeric value indicating the number assignment of a particular pin with numbering starting at 0. In some situations the letter "U" or "L" is used to indicate that the pins are assigned to the upper or lower byte of a two-byte data interface. In devices where the standard supports an optional 9th bit that may be used as a parity bit, the suffix P may be used in lieu of a numeric value. In devices where data bit groupings have independent control, an additional suffix "x" is applied. "x" takes the values of a, b, c, etc.
The outputs whose states represent the data read from the selected cells. When the device is not selected or enabled, the outputs are usually in a floating (Z, high-impedance) state. When the numbering of the data outputs is significant for device operation, the data outputs are numbered beginning with 0. In devices where data bit groupings have independent control, an additional suffix "x" is applied. "x" takes the values of a, b, c, etc.
The mix of 1s and 0s in the memory and their physical or logical positions.
A value that is either observed or calculated.
A standby or battery mode of operation in which the integrity of stored data is maintained although the supply voltage is below that specified for reading or writing.
The supply current in the data-retention mode.
The supply voltage in the data-retention mode.
Synonym for "retention time".
An operation including one data cycle or at least one data change, in which data is written into an array.
The input of a device having both serial and parallel access ports that, depending on the state of one or more of the other control lines of the device, either enables an internal data transfer between the serial and parallel port circuitry or enables the data outputs of the parallel port.
A theoretically exact point, axis, or plane that is established by tooling and is used in conjunction with a datum feature. The location or geometric characteristics of features of a part are established in relation to the datum.
The physical portion of a part that, in conjunction with suitable tooling, establishes the datum.
NOTE A centerline, by itself, cannot be a datum. It must be the centerline of a physical feature such as a hole or boss, etc. In these cases, it is the diameter of the hole or the width of the boss that is designated as the datum. The point of reference is the centerline of these physical features.
See "diagnostic clock".
A circuit that produces, from a dc input, a dc output that is proportional to a control input.
The maximum dc voltage amplitude of extraneous signal that can be algebraically added to the noise-free worst-case input level without causing the output voltage to deviate from the allowable logic voltage level.
The total dc power supplied to a device less any power delivered from the device to a load.
A terminal that is to be connected to a dc circuit.
A test during which only steady-state voltages and currents are applied to the device.
NOTE DC tests are generally used to determine input levels, output levels, or dissipation characteristics of devices.
The point on the gate characteristic VFG = f(IFG) at which, for continuously rising gate current or gate voltage, the thyristor switches from the off state to the on state.
A matrix of logic elements that selects one or more output channels according to the combination of input signals present. (Ref. ANSI/IEEE Std 100.)
A localized imperfection or deviation from the designed construction that affects function.
The number of defects on a chip divided by its area.
A failure found during tensile pull of flip chip solder joints, where the solder bump interconnection metallization is at least partially removed from either the substrate or the die, with the solder bump remaining continuous.
The time interval between a reference point on one waveform and a reference point on another waveform.
(2) (between input and output): The time interval between a transition at an input and a resultant change at an output.
(3) (of an integrated circuit) (td, tdr, and tdf): The time interval between a step-function change of the input signal level and the instant at which the magnitude of the output signal passes through a specified value (normally 10% for tdr or 90% for tdf) close to its initial value. (Ref. IEC 748‑3.)
(4) (of a transistor) (td): (A) The time interval from the point at which the leading edge of the input pulse has reached 10% of its maximum amplitude to the point at which the leading edge of the output pulse has reached 10% of its maximum amplitude.
(B) Synonym for "current delay time, tdi".
The time interval between the instant when the digital input changes and the instant when the analog output passes a specified value that is close to its initial value, ignoring glitches.
NOTE For a multiplying digital-to-analog converter, the full term and the additional subscript d must be used to distinguish between the digital and the reference delay times.
The time interval between the instant when a step change of the reference voltage occurs and the instant when the analog output passes a specified value that is close to its initial value.
An assessment of the metrics established to evaluate delivery of product.
Synonym for "space-charge region, collector(-base)".
Synonym for "space-charge region, emitter(-base)".
The operation of a field-effect transistor such that changing the gate‑source voltage from zero to a finite value decreases the magnitude of the drain current. (Ref. IEC 747‑8.)
A field-effect transistor having appreciable channel conductance for zero gate-source voltage; the channel conductance may be increased or decreased according to the polarity of the applied gate-source voltage. (Ref. IEC 747‑8.)
The process of applying a material to a substrate by means of vacuum, electrical, chemical, screening, or vapor methods.
The deposition of conductive, resistive, insulating, or semiconductor films onto a substrate from a source material in the vapor phase by physical deposition or chemical reaction.
The practice of using an electronic device in a narrower environmental and/or operating envelope than its manufacturer-designated limits.
An absorbent material used to maintain a low relative humidity.
A software description of a functional block describing the function and performance.
(1) An efficient method of experimentation that identifies factors that affect the mean and variation with minimum testing.
(2) A systematic approach to varying the input-controllable variables in the process and analyzing the effects of these process variables on the outputs. When employed in conjunction with statistical process controls, it can minimize process variability.
The basic rules and regulations for circuit design with electrical and geometrical parameters specified for the range of application conditions and time.
A functional fault for which a test pattern can be created that will always cause the effects of the fault to be observable at an externally accessible node.
A functional fault that causes effects that are observed at an externally accessible node when the circuit is exercised by the existing test pattern.
A diode, often associated with microwave circuits, that converts rf energy into dc or video output.
The distance between the intended contact point of a terminal and the established seating plane or regression plane.
NOTE Contrast with "deviation from planarity".
The difference in height between the highest point and the lowest point on the package body bottom surface measured with respect to the seating plane.
NOTE Contrast with "deviation from coplanarity".
A structural description using circuit elements as primitives.
A condition that results when molten solder coats a surface and then recedes to leave irregularly-shaped mounds of solder that are separated by areas that are covered with a thin film of solder and with the basis metal not exposed. (Ref. IPC‑T‑50.)
An alternative term for "thyristor, bidirectional diode".
NOTE Most devices designated as "diac" have been three-layer devices (npn or pnp), but others have had five layers. Some early versions were unidirectional, and a 1975 IEEE definition included them as well as bidirectional types.
The input that, on some devices, invokes and controls any built-in diagnostic test features.
Plural of "die".
Synonym for "chip (1)".
See "die bond".
A central metalplate, often used in a semiconductor package to support the active device.
The interface between the die and the die attach adhesive and/or the die attach adhesive and the die attach substrate. (Refer to Type II in Annex A of J‑STD‑035.)
The process or method of physically mounting a chip on a surface, substrate, header, etc.; also known as "die attach(ment)" or "chip attach(ment)".
A failure found in tensile pull of flip chip solder joints, where the body of the die is fractured and damaged before all the solder bumps are separated from it.
A chip-scale package whose area is generally equal to the area of the semiconductor device it contains.
NOTE 1 Usually, but not necessarily, some portion of the silicon IC is exposed. The device is then also an uncased device.
NOTE 2 The package size will change with changes in the size of the die.
The interface between the encapsulant and the active side of the die. (Refer to Type 1 in Annex A of J‑STD‑035.)
The particle flux density per unit energy incident on a surface; i.e., the number of radiant-energy particles incident on a surface during a given period of time divided by the product of the area of that surface, the characteristic energy of the incident particles, and the given period of time.
NOTE 1 The term "differential flux" is used in JESD89A whereas other standards use the term "differential flux density" for the same meaning.
NOTE 2 The equation "differential flux density = N/(A∙E∙t)" applies, where N, A, E, and t represent the quantities number of particles, area, energy, and time.
NOTE 3 The unit symbol (e.g., cm‑²∙MeV‑1∙s‑1) does not identify particle type. The particle name may be placed before the term, e.g., "proton differential flux", or in the spelled-out unit name, e.g., "protons per square centimeter megaelectronvolt second".
NOTE 4 The use of the terms "spectral flux" and "spectral flux density" for this concept is deprecated because "spectral" usually applies only to a specific wavelength, wavelength band, or function of wavelength.
A pair of ungrounded input terminals between which a signal is applied.
The voltage applied between two input terminals of a circuit.
A line receiver that has a differential input.
A pair of ungrounded output terminals between which the output signal appears.
The voltage between two output terminals of a circuit.
θ = dT/dP
This quantity is used during the current ramp and convergence to target temperature segments of the test algorithm.
A video amplifier with differential input and differential output terminals.
A process used to introduce desired impurities into a semiconductor crystal to alter its electrical properties; it is accomplished by introducing suitable dopants to the surface of the semiconductor wafer under precisely controlled conditions, usually at high temperatures.
The movement of charge carriers caused only by a charge carrier concentration gradient.
NOTE In the case of transfer across a p‑n junction, the amount of transfer depends on the internal electric field resulting from the built-in electric field and applied bias.
A converter that represents a limited number of different digital input codes by a corresponding number of discrete analog output values.
NOTE Examples of input code formats are straight binary, 2s complement, and binary‑coded decimal.
See "dual-in-line memory module".
Synonym for "diode, Schottky".
Synonym for "diode, Schottky".
A diode formed by depositing a metal film on a semiconductor surface of sufficiently high resistivity to form an energy barrier.
NOTE A Schottky diode is sometimes used as part of a bipolar transistor structure.
In its simplest form, any p-n junction but, in microcircuits, often a modified bipolar transistor.
NOTE Modifications include shorting the base to the collector, shorting the emitter to the collector, using the emitter-base diode with the collector open, or using the collector-base diode with the emitter open.
See "dual-in-line package".
The time interval between the transition of the disabling signal and the instant when the data-retention mode is entered.
NOTE This interval is defined with respect to specified reference points on the chip-enable and supply-voltage waveforms.
The time interval between the transition of the disabling signal and the instant when the supply current has decreased from its active value to its maximum standby value.
NOTE This interval is defined with respect to specified reference points on the chip-enable and supply-current waveforms.
The propagation time between specified reference points on the input and output voltage waveforms with the output changing from the defined high level to a high-impedance (off) state.
NOTE 1 Open-collector, open-emitter, open-drain, and open-source outputs are collectively referred to as open-circuit outputs. For the purposes of these definitions, the subclassification H-type is used for pnp open-collector, npn open-emitter, p‑channel open-drain, and n-channel open-source outputs because, without the aid of external components, the only on-state level they can produce is the high level. The subclassification L-type is used for npn open-collector, pnp open-emitter, n-channel open-drain, and p‑channel open-source outputs for analogous reasons.
NOTE 2 Because H-type open-circuit outputs are used with pull-down components that cause the outputs to go low when the outputs are turned off, the term "high-to-low-level propagation time" and the symbol tPHL are frequently used with these outputs for this parameter.
The propagation time between specified reference points on the input and output voltage waveforms with the output changing from the defined low level to a high-impedance (off) state.
NOTE 1 See note 1 to "disable time from the high level …".
NOTE 2 Because L-type open-circuit outputs are used with pull-up components that cause the outputs to go high when the outputs are turned off, the term "low-to-high-level propagation time" and the symbol tPLH are frequently used with these outputs for this parameter.
The time interval between the transition of the disabling signal and the cessation of the affected operation.
The propagation time between specified reference points on the input and output voltage waveforms with the output changing from either of the defined active levels (high or low) to a high-impedance (off) state.
The transition time between specified reference points on the output voltage waveform with the output changing from the defined high level to a high-impedance (off) state.
NOTE 1 See note 1 to "disable time from the high level …".
NOTE 2 Because H-type open-circuit outputs are used with pull-down components that cause the outputs to go low when the outputs are turned off, the term "high-to-low-level transition time" and the symbol tTHL are frequently used with these outputs for this parameter.
The transition time between specified reference points on the output voltage waveform with the output changing from the defined low level to a high-impedance (off) state.
NOTE 1 See note 1 to "disable time from the high level …".
NOTE 2 Because L-type open-circuit outputs are used with pull-up components that cause the outputs to go high when the outputs are turned off, the term "low-to-high-level transition time" and the symbol tTLH are frequently used with these outputs for this parameter.
Change in color caused by residue left over from processing or by chemical attack or heat.
A state in a switch device characterized by a high series impedance of the designated electrical path.
Synonym for "nonconformance" and "nonconformity (2)".
Material that does not conform to specifications.
A semiconductor device that is specified to perform an elementary electronic function and is not divisible into separate components functional in themselves.
NOTE 1 Diodes, transistors, rectifiers, thyristors, and multiple versions of these devices are examples. Other semiconductor structures having the physical complexity of integrated circuits but performing elementary electronic functions (e.g., complex Darlington transistors) are usually considered to be discrete semiconductor devices.
NOTE 2 If a semiconductor device is not considered to be an integrated circuit in both complexity and functionality, it is considered to be a discrete device.
A technique for interconnecting subarrays on a single wafer in which each subarray is electrically tested by probing and the desired array function is attained by the use of a metallization pattern that connects only usable subarrays.
The ability of the measuring equipment to differentiate between characteristic values. The equipment discrimination should be small (e.g., less than 10%) compared to the process variability and/or control limits.
A package shaped like a disk or button whose terminals exit radially from the periphery of the disk (like spokes of a wheel) or axially from the center of the disk.
An atomic imperfection or fault in the crystalline lattice structure.
NOTE 1 The two types are edge dislocations (if a row of atoms is removed or displaced and the slippage is at right angles to the displacement) and screw dislocations (if the slippage is parallel).
NOTE 2 If dislocations appear at the surface of the crystal, they are sometimes referred to as surface dislocations.
Displacement of atoms in the silicon lattice caused by their interaction with incident neutrons, protons, or other energetic particles or ions.
The act of determining the future use of nonconforming material, e.g., scrap, use-as-is, retest, rework, other.
The loss or removal of metallization from an area on the basis or substrate material during immersion in molten solder.
A model constructed from primitive models, each having specified delay.
See "data input".
See "design of experiments".
A chemical element that is introduced into the lattice structure as an impurity to form desired properties.
NOTE Examples are phosphorus and boron used to create n- and p-regions, respectively, in silicon.
The catastrophic failure of a circuit caused by the very large currents produced by a high-intensity pulse of ionizing radiation.
The disruption of a device caused by a high-intensity pulse of ionizing radiation that produces a change in stored data, a change of operating state, or a transient output signal that is large enough to affect other circuit elements.
A read transfer in an array that contains two full SAM data registers that are used alternately. Each one is loaded while the contents of the other is being transferred to the SDQ(n) port. The selection of the two SAM registers is automatic.
A technology for producing silicon-gate metal-oxide semiconductor field-effect transistors such that 1) the threshold voltage, VT, is determined by the intersection of two doping profiles, and 2) the device channel length is defined by the diffusion characteristics rather than by a photolithographic self-aligned gate structure.
A printed circuit board assembly with components mounted on both sides of the board.
A circuit in which the current flows in both directions from each terminal of the alternating-voltage circuit to the rectifier circuit elements connected to each terminal.NOTE The terms “single-way” and “double-way” provide a means for describing the effect of the rectifier circuit on current in the transformer windings connected to the rectifier circuits. Most rectifier circuits may be classified into these two general types. Many double-way circuits are also referred to as bridge circuits.
A character string or binary element string that, in a given system, has twice the length of a word.
See "dual-port memory".
See "dual-port static RAM".
See "input/output data mask".
See "data input/output".
A region into which majority carriers flow from the channel.
The direct current into the drain terminal.
The direct current into the drain terminal of a depletion-type transistor with a specified reverse gate-source voltage applied to bias the device to the off-state.
The dc voltage between the drain terminal and the gate terminal.
The drain current when the transistor is biased in its off state.
NOTE ID(leak) may have contributions from channel off-state current, gate-induced drain leakage, and drain-to-gate tunneling currents.
The primary power voltage on MOS devices that require a potential that differs from the normal system logic voltage. The term VDD is used interchangeably with VCC on devices that use 5‑V supplies.
A collection region that acquires principal-current charge carriers from a channel, the current being due to a voltage applied to the drain.
NOTE This definition applies for the actual operating mode of the device regardless of the name of any associated terminal.
The capacitance between the drain and source terminals with the gate terminal connected to the guard terminal of a three-terminal bridge.
The dc voltage between the drain terminal and the source terminal.
The dc supply voltage applied to a circuit connected to the drain terminal.
The specified externally available point of connection to the drain region.
See "dynamic (random-access) memory".
The maximum absolute change in a parameter over a period of time.
NOTE The change may or may not be normalized to the initial value of the parameter. The specific term should be "(parameter) drift".
An amplifier or gate with increased ability to drive a load.
See "double-buffered read transfer".
See "special-function enable input".
See "data-transfer/output-enable input"
Synonym for "tetrode field-effect transistor".
A device package configuration that has two parallel rows of pins that are spaced nominally 0.3 inch, 0.4 inch, or 0.6 inch apart with the pins on 0.1-inch centers.
NOTE See also "in-line package".
A packaging arrangement of memory devices on a socketable substrate.
Any memory that has two essentially identical data ports.
A static RAM that contains two sets of identical random-access address and data ports.
Data transmission in both directions simultaneously. (Ref. ANSI X3.172.)
Device under test.
The magnitude of the deviation in time duration between the primary threshold crossing and the secondary threshold crossing in a cycle over a random sample of cycles.
The ratio of the power-on time duration per cycle to the total cycle time.
NOTE Power duty cycle is usually expressed as a percentage.
See "design validation/verification".
The incremental phase offset between the input reference clock and the feedback input signal of a phase-locked loop (PLL) resulting from modulation of the input reference clock.
A dynamic memory that permits access to any of its address locations in any desired sequence with similar access time to each location.
The range of useful linear operation expressed as the ratio of the saturation input signal to the noise equivalent signal.
A volatile read/write memory in which the cells require the repetitive application of control signals generated inside or outside the integrated circuit to retain stored data. (Adapted from IEC 748‑2.)
NOTE 1 The words "read/write" may be omitted from the term when no misunderstanding is likely.
NOTE 2 Each repetitive application of the control signals is normally called a refresh operation or cycle.
NOTE 3 A dynamic memory can use static addressing or sensing circuits.
NOTE 4 Contrast with "static (read/write) memory".
A two-dimensional bar code matrix symbol.
A physical anomaly that adversely affects function or performance.
A physical defect created by the natural changes in the properties of materials over time that is manifested after some period of operation.
A fracture in the far-back-end-of-line (FBEOL) die structure.
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