See "column address".

See "content-addressable memory".

The natural variation of the process due to common causes.

A measure of the relationship between the specification limits and the capability. See EIA QB6, Guideline on the Use and Application of Cpk and The Use and Abuse of Cpk by Berton H. Gunter.

A pocket tape, tray, tube, or other fixture used to store and transport finished packaged components.

See "column enable".

The temperature measured at a specified location on the case of a device.

Synonym for "read latency".

(1) The n‑type region to which the forward current flows within a semiconductor diode.

NOTE    In Schottky diodes, usually the barrier metal replaces the p‑type semiconductor region and the remaining semiconductor region is n‑type; however, some Schottky diodes have been made with the barrier metal replacing the n‑type semiconductor region, in which case the remaining semiconductor region is p‑type.

(2) A circuit element to which negative bias is applied.

The terminal connected to the n‑type region of the p‑n junction or, when two or more p‑n junctions are connected in series with the same polarity, to the extreme n‑type region.

NOTE 1 See note to "cathode".

NOTE 2 This definition does not apply to current-regulator diodes.

NOTE 3 For voltage-reference diodes, any temperature-compensating diodes that may be included shall be ignored in the determination of the anode terminal.

(2) (of a current-regulator diode): The terminal from which current flows into the external circuit when the diode is biased to operate as a current regulator.

(3) (of a unidirectional diode thyristor): The terminal from which the current flows to the external circuit when the thyristor is in the on state.

(4) (of a unidirectional triode thyristor): The main terminal from which the principal current flows to the circuit being controlled when the thyristor is in the on state.

NOTE A second cathode terminal may be provided for connecting to the control circuit of a p‑gate thyristor.

A package containing a cavity that is intended to be occupied by a chip.

See "charged-device model".

See "column enable".

A tool that automatically generates the physical layout to meet the specified parameters and that may generate a symbol and timing and functional models.

A functional unit that consists of one or more processors and their internal storage. (Ref. ANSI X3.172.)

See "cumulative fraction failing".

An alteration to the product process; which may be major or minor: a) major change: a change that may affect the form, fit, or function of the product or adversely affect the quality or reliability of the product, or b) minor change: a change that does not affect the form, fit, function, or reliability of the product.

A gate array configuration that contains a predetermined and dedicated area for logic interconnection.

A control region through which the principal current passes and in which the concentration of principal-current charge carriers is determined by voltage applied to a gate, the principal current being the result of an applied drift field.

NOTE This definition applies for the actual operating mode of the device regardless of the name of any associated terminal.

(2) (of a JFET): A control region through which the principal-current charge carriers pass and whose cross-section is determined by the voltage applied to a gate, the principal current being the result of an applied drift field.

NOTE This definition applies for the actual operating mode of the device regardless of the name of any associated terminal.

The time at which F(t) equals (1 - e^-1) (≈63.2%).

A description of the characteristics of a product or process by mathematical modeling, design of experiments, or statistical data evaluation.

A charge-coupled device in which an optical image is converted into packets of charge that can be transferred as the electrical analog of the image.

The maximum amount of charge that can be stored in a potential well and transferred without overflow into adjacent wells.

(1) A dc-to-dc converter in which a capacitor is charged from a voltage source and then electrically reconnected in series with that source to make available a voltage greater than that of the source.

NOTE This type of dc-to-dc converter is sometimes called a voltage doubler or, when several stages are cascaded, a voltage multiplier.

(2) A dc-to-dc converter in which a capacitor is charged from a voltage source and then electrically reconnected to make available a voltage whose polarity is opposite to that of the source.

A device in which operation depends on the movement of discrete packets of charge along or beneath the semiconductor surface or through the interconnections on the semiconductor surface.

The fraction of the signal charge that fails to be transferred from one storage region to the next storage region.

NOTE A synonym is "incomplete charge-transfer coefficient".

The time required to move a specified fraction of a charge packet from one storage region to the next.

A form for data collection.

See "die bond".

A package whose chip cavity or mounting area occupies a major fraction of the package area and whose terminals consist of metal pad surfaces (on leadless versions) or leads formed around the sides and under the package or out from the package (on leaded versions).

NOTE The term "chip carrier" has been replaced by "quad flatpack" (for terminals on three or four sides) and "small-outline package" (for terminals on one or two sides).

A control input that, when active, permits operation of the integrated circuit and, when inactive, causes the integrated circuit to be in a reduced-power standby mode. (Ref. IEC 748‑2.)

NOTE A chip-enable input is a clock or strobe input that significantly affects the power dissipation of the integrated circuit. For example, it may be the cycle control input of a dynamic memory or a power-reduction input of a static memory.

A chip whose electrical terminations are on the side opposite the one that is intended to be attached to the mounting substrate.

The interaction between the semiconductor package stresses and the semiconductor device.

The input(s) that, when any one is false, causes the device to be disabled without any significant change in the power consumption. When deselected, the outputs go to the inactive state (floating, Z) for MOS and TTL devices and low (L) for ECL devices, and the device becomes insensitive to a write command. In devices where data bit groupings have independent control, an additional suffix "x" is applied. "x" takes the value of "a", "b", "c", etc.

Any constituent part of a circuit that contributes directly to its operation and performs a definable function.

NOTE 1 Examples include transistors, resistors, capacitors, inductors, and interconnections.

NOTE 2 The definition in JESD12-1B excludes interconnections.

A circuit element that is an unavoidable adjunct of one or more other circuit elements.

A sequence of stimuli that set internal nodes of a circuit to a predictable state.

See "complex-instruction-set computer".

See "clock enable".

A package for high-current devices, in the form of a cylinder with a flat, circular, high-current terminal on each end, that is intended to be clamped between two busbars acting as heat sinks.

To preset a storage or memory device to a prescribed state, usually that denoting zero. (Ref. IEEE Std 100.)

NOTE In the field of nonvolatile memories, clear conventionally means to set the outputs of the memory to the high logic level.

The timed sequence of signals necessary to clear the memory.

The corruption of data in one location caused by the clearing of data at another location.

The structure by which clock signals are distributed within a device.

In certain synchronous memory devices, a logic level input that enables the clock input and allows it to fulfill its defined function.

The difference in the arrival times of a common clock edge at any two circuit elements.

A technology for combining complementary metal-oxide-semiconductor (CMOS) field-effect devices and double-diffused metal-oxide-semiconductor (DMOS) field-effect transistors in a single-chip integrated circuit.

A heat absorber usually operating at some known or fixed temperature.

A semiconductor junction in an operating condition in which the net flow of charge carriers of each type across the junction is in the direction from the region where they are minority carriers to the region where they are majority carriers, i.e., in the direction of the force resulting from the internal electric field.

The product of the intrinsic base resistance and collector capacitance under specified small-signal conditions.

The dc current into the collector terminal when it is biased in the reverse direction with respect to the base terminal and the emitter terminal is open-circuited.

The junction across which the polarity of the voltage reverses when switching occurs. (Ref. EIA‑397.)

A collection region that acquires principal-current charge carriers from a controlling base region through an associated collecting junction.

NOTE This definition applies for the actual operating mode of the device regardless of the name of any associated terminal. In the normal operating mode, this functional region is located in the collector region; in the inverse operating mode, it is located in the emitter region.

The specified externally available point of connection to the collector region.

In an address-multiplexed DRAM, the address field that is captured by the column enable clock, CAS. When the column address numbering is significant for device operation, the addresses are numbered beginning with 0.

A functional fault that is not affected by the sequence of the input stimuli.

A source of natural variation that affects all the individual values of the process output being studied. In control chart analysis it appears as part of the random process variation.

The range of common-mode input voltage that, if exceeded, will cause the total harmonic distortion of the output signal resulting from the common-mode input to exceed a specified maximum value.

The ratio of the differential voltage amplification to the common-mode voltage amplification.

The real part of the corresponding admittance. See y_fs, y_is, y_os, and y_rs. Symbols in the forms of g_xx and y_xx(real) are equivalent.

A digital-to-analog converter whose transfer function complies with a compression or expansion law.

NOTE 1 The corresponding analog-to-digital coverter normally consists of such a companding DAC and additional external circuitry.

NOTE 2 The compression or expansion law is usually a logarithmic function, e.g., A‑law or μ‑law.

(1) The change in a temperature-sensitive parameter divided by the change in a dependent heating-condition parameter.

(2) For an integrated circuit, the change in temperature-sensing diode forward junction voltage under measurement conditions divided by the change in heating current, ΔV_F/ΔI_H. This allows for thermal comparison of one device to another when the heating voltage remains constant.

A technology for combining p‑channel and n-channel metal-oxide-semiconductor field-effect transistors in a single-chip integrated circuit.

A microcomputer or microprocessor that performs multiple tasks per complex instruction, usually requiring multiple clock cycles.

The permissible range of output current within which the specifications are valid.

A component in which at least one circuit element is an active circuit element.

An integrated circuit, completed or partially completed, that serves as a component of a hybrid integrated circuit.

A component in which all circuit elements are passive.

A packaged semiconductor device.

The part of an alternating-voltage cycle during which the current flows in the forward direction.

NOTE The forward period is not necessarily the same as the conducting period because of circuit parameters and semiconductor rectifier diode characteristics.

A charge-coupled device that uses doped regions between the potential wells and hence becomes a hybrid between the charge-coupled device and a bucket-brigade device.

An electrically conducting element that functions as a pathway between other elements, including terminals, and whose primary purpose is to conduct electric current in a confined manner.

NOTE The connection may either consist of a separate conductive entity such as a wire or metallic film or be an integral part of the body.

The gate-source voltage at which the drain current is equal to a constant current, appropriate for a given technology, times the ratio of gate width (W) to gate length (L). V_T(ci) can be calculated using

V_T(ci) = V_GS (at I_D = I_D0 W/L)

where

W and L are the gate width and gate length as printed on the wafer;

I_D0 is selected for a given technology such that V_T(ci) is in the subthreshold region of the device. For N-MOSFET devices, JESD28-A suggests 0.1 μA; for P-MOSFET devices, JESD60 suggests -0.025 μA.

Interim action(s) taken to minimize the effects of component problems on customers until corrective actions are implemented.

The methodology whereby quality improvement tools (e.g., statistical process control (SPC), Ishikawa diagram, design of experiments (DOE), etc.) are applied to a process to improve measurable attributes (e.g., repeatability, efficiency, predictability, etc.).

A bus carrying the signals that regulate system operations. (Ref. ANSI X3.172.)

A graphic representation of a process characteristic showing plotted values of some statistic gathered from that characteristic, a central line, and one or two statistically derived control limits. Two basic uses are to determine whether a process has been operating in statistical control and to aid in maintaining statistical control.

The ability of a node to be established at specific logic state(s) by applying stimuli to the circuit's externally accessible node(s).

A semiconductor power-control module (thyristor SPCM, transistor SPCM, thyristor-diode SPCM, or transistor-diode SPCM) with internal control-signal processing circuitry that may have provisions for external adjustment.

A corrective action system based on a feedback procedure.

The terminals to which the external control signal is applied.

The period of time between exiting the constant-rate current ramp and convergence to the target test temperature.

The maximum available luminous or radiant flux output divided by the total input power.

(2) (of a photovoltaic diode): The maximum available power output resulting from photovoltaic operation divided by the total incident radiant flux.

The number of conversions per unit time.

NOTE 1 The maximum conversion rate should be specified for full resolution.

NOTE 2 The conversion rate is usually expressed as the number of conversions per second.

NOTE 3 Because of settling or recovery time, the maximum specified conversion rate is smaller than the reciprocal of the worst-case conversion time.

Warpage resulting in the package corners being closer to the seating plane than the center of the bottom surface of the package.

The condition where an interrupted surface, or two or more surfaces, have all their elements in one plane. The tolerance zone is established by two parallel planes between which all elements of the interrupted surface must lie. This is analogous to the flatness requirement for a continuous surface.

NOTE See also "deviation from coplanarity".

A processing unit that extends the capabilities of its main processor, directly accesses the memory of that processor, and does not operate autonomously. (Ref. IEC 824.)

Action taken to eliminate the root cause(s) of an existing nonconformance or other undesirable situation in order to prevent recurrence.

A failure due to an inherent defect in an electronic device during early-life-failure (ELF) stress tests.

NOTE Failures due to electrical overstress (EOS), electrostatic discharge (ESD), mechanical damage, etc., are not counted, but the failing devices are considered to have completed testing through the last successful readout when computing device-hours.

A line of fracture in a package without complete separation.

Pertaining to that which significantly impacts product quality and/or reliability.

In semiconductor devices, any potential physical failure mechanism that exhibits one or more of the following: intermittency (e.g., bond lifts), increasing failure rate (e.g., electromigration), and inconsistent or unpredictable failure kinetics (e.g., stress-induced metal voiding).

A node in the process flow whose output has a significant impact on the process.

The pulling apparatus on the tensile pull tool.

The number of events per unit fluence.

NOTE If the depth of the sensitive volume is small compared to its lateral dimensions, the SEE cross section (σ) can be calculated as follows:

σ = number of events / (fluence × cos θ )

where θ is the angle of incidence of the ion.

See "customer-specific standard product".

See "comparison unit".

The probability that a device will have failed by a specified time t₁ or the fraction of units that have failed by that time.

NOTE 1 The value of this function is given by the integral of f(t) from 0 to t₁.

NOTE 2 This value is generally expressed in percent (%) or in parts per million (ppm) for a defined early-life failure period.

NOTE 3 The abbreviation CDF is often used; however, the symbol F(t) is preferred.

The total fraction failing based on the starting sample size over a given time interval.

NOTE This value is generally expressed in percent (%) or in parts per million (ppm).

The probability that a device will still be functional at a specified time t₁ or the fraction of units surviving to that time.

NOTE R(t) = 1 - F(t).

The time interval during which an input pulse that is switching the transistor from a nonconducting to a conducting state rises from 10% of its peak amplitude and the collector current waveform rises to 10% of its on-state amplitude, ignoring spikes caused by interaction with other components or parasitics, e.g., freewheeling-diode recovery current and parasitic inductance.

The current density in the narrowest region of the test structure at the initial application of the forcing current for SWEAT stressing.

The instantaneous total value of alternating current into the terminal indicated by the subscript.

A diode that limits current to an essentially constant value over a specified voltage range.

Graphic symbol (ref. IEEE Std 315):

The time interval during which the collector (or drain) current changes from 10% to 90% of its peak off-state value, ignoring spikes caused by interaction with other components or parasitics, e.g., freewheeling-diode recovery current and parasitic inductance.

The voltage that is a function of the load current and is normally used for control of the current-limiting circuitry.

The sum of current turn-off delay time and current fall time, i.e., t_d(off)i + t_fi.

A component that has been soldered to or de-soldered from a circuit board or other mounting surface by the customer.

An integrated circuit developed or produced to conform to unique requirements.

NOTE The terms "full custom" and "semicustom" refer to layout methodologies. The choice of term is subjective, depending on the interpretation of the ratio of unique layouts to standard macrocell layouts from a library.

(1) A sequence of operations in which one set of events is completed.

(2) Any set of operations that is repeated regularly in the same sequence.

NOTE The operations may be subject to variations on each repetition. (Ref. ANSI X3.172.)

The time interval between the start and the end of a cycle.

NOTE The cycle time is the actual time interval between two signal events and is determined by the system in which the digital circuit operates. A minimum value is specified that is the shortest interval that must be allowed for the digital circuit to perform a specified function (e.g., read, write, etc.) correctly.

The dc current into the collector terminal when it is biased in the reverse direction* with respect to the emitter terminal, and the base terminal is, respectively,

• open-circuited.

• short-circuited to the emitter terminal.
• returned to the emitter terminal through a specified circuit.

• returned to the emitter terminal through a specified resistance.

• returned to the emitter terminal through a specified voltage.

*For these parameters, the collector terminal is considered to be biased in the reverse direction when it is made positive for npn transistors or negative for pnp transistors with respect to the emitter terminal.

The dc current into the collector terminal when it is biased in the reverse direction* with respect to the emitter terminal, and the base terminal is, respectively,

• open-circuited.

• short-circuited to the emitter terminal.
• returned to the emitter terminal through a specified circuit.

• returned to the emitter terminal through a specified resistance.

• returned to the emitter terminal through a specified voltage.

*For these parameters, the collector terminal is considered to be biased in the reverse direction when it is made positive for npn transistors or negative for pnp transistors with respect to the emitter terminal.

The dc current into the collector terminal when it is biased in the reverse direction* with respect to the emitter terminal, and the base terminal is, respectively,

• open-circuited.

• short-circuited to the emitter terminal.
• returned to the emitter terminal through a specified circuit.

• returned to the emitter terminal through a specified resistance.

• returned to the emitter terminal through a specified voltage.

*For these parameters, the collector terminal is considered to be biased in the reverse direction when it is made positive for npn transistors or negative for pnp transistors with respect to the emitter terminal.

A set of data for which a portion of the test samples had testing discontinued prior to failing or survived until the end of the test.

The difference in luminance (“brightness”) between the mark and the surrounding device surface.