JEDEC Memory Workshops: DDR5, NVDIMM-P, DRAM Tutorial

Save the date for an unparalleled opportunity to learn about JEDEC memory standards, taught by industry experts involved in their development.  Choose one or two events, or attend all three!  Online registration and detailed agendas will be available this spring.  Location: Santa Clara, CA.

  • Monday, October 30, 2017: DRAM Tutorial
  • Tuesday-Wednesday, October 31-November 1, 2017: DDR5 Workshop
  • Thursday, November 2, 2017: NVDIMM-P Workshop

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