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JEDEC Committee:
Multiple Chip Package JC-63
JC-63 defines/proposes standards for mixed-technology MCP that address unique electrical, mechanical, test, and architecture issues relating to die-to-die design and manufacturing for commercial applications.
MCP is defined as multichip package, a single package that contains multiple dice, including memory-memory, logic-memory, logic-logic, and/or passive components.
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Recent Documents
| Title | Document # |
Date |
|---|---|---|
| Multichip Packages (MCP) Configurations | MCP3_12_01 | Feb 2010 |
| Package-on-Package (PoP) and Internal Stacked Module (ISM) | MCP3_12_02 | Feb 2010 |
| Silicon Pad Sequence (x16/x32 LPDRAM, x16 PSRAM, x16 NAND). Item JC-63-029 | MCP3_12_03 | Nov 2006 |
| MCP Overview | MCP3_12_00 | Jun 2006 |
Join JC-63
Interested in JC-63’s MCP mission? Find out more about the benefits of JEDEC membership today.
Membership Information
Committee Meetings
| Toronto | 7 - 11 Jun 2010 |
| Denver | 13 - 17 Sep 2010 |
| San Francisco | 6 - 10 Dec 2010 |
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