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JEDEC Committee:
DRAM Modules JC-45
The scope of JC-45 is to develop standards for DRAM modules, cards, and socket interfaces. These standards are to address architectural, electrical, test, and SPD issues relating to memory design and manufacturing for commercial applications.
Memory module is defined as a single or multiple PCBs that predominantly include multiple memory, logic, and passive devices in a planar or 3D layout for use with sockets.
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- JC-45 and Subcommittees
Recent Documents
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Subcommittees
| Status (status) | ||
|---|---|---|
| JC-45.1 | Registered DRAM Modules | |
| JC-45.3 | Small DRAM Modules | |
| JC-45.4 | Fully Buffered DRAM Modules | |
| JC-45.5 | Module Interconnect | |
| JC-45.6 | Hybrid Modules |
Join JC-45
Interested in JC-45’s DRAM Modules mission? Find out more about the benefits of JEDEC membership today.
Membership Information
Committee Meetings
| Denver | 3 - 7 Jun 2013 |
| Austin | 9 - 13 Sep 2013 |
| Maui | 9 - 13 Dec 2013 |
| Newport Beach | 3 - 7 Mar 2014 |
| Montreal | 15 - 19 Sep 2014 |
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