JEDEC Committee:

DRAM Modules JC-45

The scope of JC-45 is to develop standards for DRAM modules, cards, and socket interfaces. These standards are to address architectural, electrical, test, and SPD issues relating to memory design and manufacturing for commercial applications.

Memory module is defined as a single or multiple PCBs that predominantly include multiple memory, logic, and passive devices in a planar or 3D layout for use with sockets.

Subcommittees

Status (status)
JC-45.1 Registered DRAM Modules
JC-45.3 Small DRAM Modules
JC-45.4 Fully Buffered DRAM Modules
JC-45.5 Module Interconnect
JC-45.6 Hybrid Modules

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Membership Information

Committee Meetings

Munich 2 - 6 Jun 2014
Montreal 15 - 19 Sep 2014
Orlando 8 - 12 Dec 2014
Seoul 2 - 6 Mar 2015
Vancouver 1 - 5 Jun 2015

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