The products within JC-42's scope include all memory integrated circuits and programmable logic devices, whether static or dynamic, without regard to their fabrication technology or application. Examples include large static and dynamic RAMs, ROMs, EEPROMs, and PLDs.
Activities include the development of technical information and standards pertaining to pinouts, operational characteristics including reading and writing algorithms, test parameters, characterization, and registration formats.
The committee maintains liaisons with other JEDEC committees and outside organizations to promote wide acceptance of the committee’s actions.
|Addendum No. 1 to JESD79-3 - 1.35 V DDR3L-800, DDR3L-1066, DDR3L-1333, DDR3L-1600, and DDR3L-1866||JESD79-3-1A.01||May 2013|
|GDDR5 SGRAM||JESD212A||Apr 2013|
|STANDARD MANUFACTURERS IDENTIFICATION CODE||JEP106AK||Mar 2013|
|NAND FLASH INTERFACE INTEROPERABILITY||JESD230||Oct 2012|
|DDR4 SDRAM STANDARD||JESD79-4||Sep 2012|
|DDR3 SDRAM STANDARD||JESD79-3F||Jul 2012|
|EE1004 and TSE2004 Device Specifications||SPD4_01_06||Jul 2012|
|LOW POWER DOUBLE DATA RATE 3 SDRAM (LPDDR3)||JESD209-3||May 2012|
|Annex A: Differences between JESD21C Release 22 and its predecessor JESD21C, Release 20.||AnnexA - JESD21C||Jan 2012|
|WIDE I/O SINGLE DATA RATE (WIDE I/O SDR)||JESD229||Dec 2011|
|JC-42.3B||DRAM Functions and Features|
|JC-42.4||Non-Volatile Memory Devices|
|JC-42.6||Low Power Memories|