The products within JC-42's scope include all memory integrated circuits and programmable logic devices, whether static or dynamic, without regard to their fabrication technology or application. Examples include large static and dynamic RAMs, ROMs, EEPROMs, and PLDs.
Activities include the development of technical information and standards pertaining to pinouts, operational characteristics including reading and writing algorithms, test parameters, characterization, and registration formats.
The committee maintains liaisons with other JEDEC committees and outside organizations to promote wide acceptance of the committee’s actions.
|GDDR5 MEASUREMENT PROCEDURES||JEP171||Aug 2014|
|LOW POWER DOUBLE DATA RATE 4 (LPDDR4)||JESD209-4||Aug 2014|
|NAND FLASH INTERFACE INTEROPERABILITY||JESD230B||Jul 2014|
|STANDARD MANUFACTURERS IDENTIFICATION CODE||JEP106AN||Jun 2014|
|SERIAL FLASH DISCOVERABLE PARAMETERS (SFDP)||JESD216B||May 2014|
|JC-42.6 MANUFACTURER IDENTIFICATION (ID) CODE FOR LOW POWER MEMORIES||JEP166||Mar 2014|
|EE1004 and TSE2004 Device Specifications||SPD4_01_06||Mar 2014|
|Addendum No. 3 to JESD79-3 - 3D Stacked SDRAM||JESD79-3-3||Dec 2013|
|GRAPHICS DOUBLE DATA RATE (GDDR5) SGRAM STANDARD||JESD212B.01||Dec 2013|
|HIGH BANDWIDTH MEMORY (HBM) DRAM||JESD235||Oct 2013|
|JC-42.3B||DRAM Functions and Features|
|JC-42.4||Non-Volatile Memory Devices|
|JC-42.6||Low Power Memories|