The products within JC-42's scope include all memory integrated circuits and programmable logic devices, whether static or dynamic, without regard to their fabrication technology or application. Examples include large static and dynamic RAMs, ROMs, EEPROMs, and PLDs.
Activities include the development of technical information and standards pertaining to pinouts, operational characteristics including reading and writing algorithms, test parameters, characterization, and registration formats.
The committee maintains liaisons with other JEDEC committees and outside organizations to promote wide acceptance of the committee’s actions.
|LOW POWER DOUBLE DATA RATE 4 (LPDDR4)||JESD209-4B||Mar 2017|
|STANDARD MANUFACTURERS IDENTIFICATION CODE||JEP106AU||Mar 2017|
|Addendum No. 1 to JESD79-4, 3D Stacked DRAM||JESD79-4-1||Feb 2017|
|Annex A: Differences between JESD21C Release 26 and its predecessor JESD21C, Release 26.||AnnexA - JESD21C||Jan 2017|
|NAND FLASH INTERFACE INTEROPERABILITY||JESD230C||Nov 2016|
|GRAPHICS DOUBLE DATA RATE (GDDR5X) SGRAM STANDARD||JESD232A||Aug 2016|
|JC-42.6 MANUFACTURER IDENTIFICATION (ID) CODE FOR LOW POWER MEMORIES||JEP166B||Feb 2016|
|GRAPHICS DOUBLE DATA RATE (GDDR5) SGRAM STANDARD||JESD212C||Feb 2016|
|EE1004 and TSE2004 Device Specification - Definitions of the EE1004-v 4 Kbit Serial Presence Detect (SPD) EEPROM and TSE2004av 4 Kbit SPD EEPROM with Temperature Sensor (TS) for Memory Module Applications||SPD4.1.6||Feb 2016|
|HIGH BANDWIDTH MEMORY (HBM) DRAM||JESD235A||Nov 2015|
|JC-42.3B||Functions, Features and Pinouts|
|JC-42.4||Non-Volatile Memory Devices|
|JC-42.6||Low Power Memories|