JC-40 | JEDEC

Digital Logic JC-40

The products within JC-40's scope include digital integrated circuits without regard to their fabrication technology. The committee develops the definition of test parameters and their methods of measurement, and registration formats to promote standardization of type designations.

To accomplish these functions, the committee cooperates with other JEDEC committees and organizations on matters of terms and definitions, mechanical standardization, international standardization, and government liaison. The committee also maintains liaisons with user organizations to promote wide acceptance of the committee’s output.

Search Documents related to JC-40 and Subcommittees
JC-40 and Subcommittees

Title	Document #	Date
2.5 V BiCMOS LOGIC DEVICE FAMILY SPECIFICATION WITH 5 V TOLERANT INPUTS AND OUTPUTS:	JESD70	Jun 1999
BALL GRID ARRAY PINOUT FOR 1-, 2-, AND 3-BIT LOGIC FUNCTIONS:	JESD75-4	Mar 2004
BALL GRID ARRAY PINOUTS STANDARDIZED FOR 16, 18, AND 20-BIT LOGIC FUNCTIONS USING A 54 BALL PACKAGE:	JESD75-1	Oct 2001
BALL GRID ARRAY PINOUTS STANDARDIZED FOR 16-BIT LOGIC FUNCTIONS:	JESD75-2	Jul 2001
BALL GRID ARRAY PINOUTS STANDARDIZED FOR 32-BIT LOGIC FUNCTIONS:	JESD75	Nov 1999
BALL GRID ARRAY PINOUTS STANDARDIZED FOR 8-BIT LOGIC FUNCTIONS:	JESD75-3	Jul 2001
CHIP CARRIER PINOUTS STANDARDIZED FOR CMOS 4000, HC AND HCT SERIES OF LOGIC CIRCUITS:	JESD11	Dec 1984
DEFINITION OF CDCV857 PLL CLOCK DRIVER FOR REGISTERED DDR DIMM APPLICATIONS:	JESD82	Jul 2000
DEFINITION OF CU878 PLL CLOCK DRIVER FOR REGISTERED DDR2 DIMM APPLICATIONS	JESD82-11	Sep 2004
DEFINITION OF CVF857 PLL CLOCK DRIVER FOR REGISTERED PC1600, PC2100, PC2700, AND PC3200 DIMM APPLICATIONS:	JESD82-1A	May 2004

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