The activities within JC-16’s scope include the specification of power supply voltage levels for digital integrated circuits and the definition of electrical interfaces between the components of a system. The committee scope further encompasses interface protocols, modeling, simulation, testing environments, and verification.
JC-16 also hosts efforts on operating environment specifications that are common to JC-40, JC-42, and JC-45. The committee maintains a liaison with other JEDEC committees and appropriate outside organizations, both in formulating standards and in promoting wide acceptance of the committee’s activities.
|0.6 V LOW VOLTAGE SWING TERMINATED LOGIC (LVSTL06)||JESD8-29||Dec 2016|
|MULTI-WIRE MULTI-LEVEL I/O STANDARD||JESD247||Jun 2016|
|300 mV INTERFACE||JESD8-28||Jun 2015|
|HSUL_12 LPDDR2 AND LPDDR3 I/O WITH OPTIONAL ODT||JESD8-22B||Apr 2014|
|POD135 - 1.35 V PSEUDO OPEN DRAIN I/O||JESD8-21A||Sep 2013|
|SERIAL INTERFACE FOR DATA CONVERTERS||JESD204B.01||Jan 2012|
|POD10-1.0 V PSUEDO OPEN DRAIN INTERFACE||JESD8-25||Sep 2011|
|1.2 V HIGH-SPEED LVCMOS (HS_LVCMOS) INTERFACE||JESD8-26||Sep 2011|
|POD12 ‐ 1.2 V PSEUDO OPEN DRAIN INTERFACE||JESD8-24||Aug 2011|
|POD15 - 1.5 V PSEUDO OPEN DRAIN I/O||JESD8-20A||Oct 2009|