The activities within JC-16’s scope include the specification of power supply voltage levels for digital integrated circuits and the definition of electrical interfaces between the components of a system. The committee scope further encompasses interface protocols, modeling, simulation, testing environments, and verification.
JC-16 also hosts efforts on operating environment specifications that are common to JC-40, JC-42, and JC-45. The committee maintains a liaison with other JEDEC committees and appropriate outside organizations, both in formulating standards and in promoting wide acceptance of the committee’s activities.
|HSUL_12 LPDDR2 AND LPDDR3 I/O WITH OPTIONAL ODT||JESD8-22A||Oct 2012|
|SERIAL INTERFACE FOR DATA CONVERTERS||JESD204B.01||Jan 2012|
|POD10-1.0 V PSUEDO OPEN DRAIN INTERFACE||JESD8-25||Sep 2011|
|1.2 V HIGH-SPEED LVCMOS (HS_LVCMOS) INTERFACE||JESD8-26||Sep 2011|
|POD12 ‐ 1.2 V PSEUDO OPEN DRAIN INTERFACE||JESD8-24||Aug 2011|
|POD135 - 1.35 V PSEUDO OPEN DRAIN I/O||JESD8-21||Jul 2010|
|POD15 - 1.5 V PSEUDO OPEN DRAIN I/O||JESD8-20A||Oct 2009|
|UNIFIED WIDE POWER SUPPLY VOLTAGE RANGE CMOS DC INTERFACE STANDARD FOR NON-TERMINATED DIGITAL INTEGRATED CIRCUITS||JESD8-23||Oct 2009|
|FBDIMM SPECIFICATION: HIGH SPEED DIFFERENTIAL PTP LINK AT 1.5 V||JESD8-18A||Mar 2008|
|ADDENDUM No. 5 to JESD8 - 2.5 V 0.2 V (NORMAL RANGE), AND 1.8 V TO 2.7 V (WIDE RANGE) POWER SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED DIGITAL INTEGRATED CIRCUIT:||JESD8-5A.01||Sep 2007|