Ever-increasing expectations for mobile device performance are driving the need for versatile mobile memory solutions. Users and suppliers are collaborating to develop the JEDEC standards needed to define those solutions.
LPDDR2
First published in April 2009 and updated in April 2011 by the JC-42.6 Subcommittee for Low Power Memories, the JEDEC LPDDR2 standard (JESD209-2E) offers advanced power management features, a groundbreaking shared interface for nonvolatile memory (NVM) and volatile memory (SDRAM), and a range of densities and speeds. The standard will enhance the design of such products as smart phones, cell phones, PDAs, GPS units, handheld gaming consoles, and other mobile devices by enabling increased memory density, improved performance, smaller size, overall reduction in power consumption as well as a longer battery life.
Learn more about LPDDR2 or
download JESD209-2E free of charge with registration.
LPDDR3
Published in May 2012, JESD209-3 LPDDR3 is designed to satisfy the performance and memory density demands of the latest generation of mobile devices such as smartphones, tablets, ultra-thin notebooks and similar connected devices on the newest, high-speed 4G networks. LPDDR3 offers a higher data rate, improved bandwidth and power efficiency, and higher memory densities over its groundbreaking predecessor, LPDDR2.
LPDDR3 will preserve the power-efficient features and signaling interface of LPDDR2, allowing for fast clock stop/start, low-power self-refresh, and smart array management.
Download JESD209-3 free of charge with registration.
Wide I/O
Published in December 2011 by JC-42.6, Wide I/O Mobile DRAM is a breakthrough technology that will meet industry demands for increased levels of integration as well as improved performance, bandwidth, latency, power, weight and form factor. Download JESD229 Wide I/O Single Data Rate (SDR) free of charge with registration.
Wide I/O Mobile DRAM uses chip-level three dimensional (3D) stacking with Through Silicon Via (TSV) interconnects and memory chips directly stacked upon a System on a Chip (SoC). Wide I/O is particularly suited for applications requiring increased memory bandwidth up to 17GBps, such as 3D Gaming, HD Video (1080p H264 video, pico projection), simultaneously-running applications, etc. Wide I/O will provide the ultimate in performance, energy efficiency and small size for smartphones, tablets, handheld gaming consoles and other high performance mobile devices.
Memory MCP
Memory Multiple Chip Package (MCP) stacks multiple chips into a single package, offering increased spatial density and performance benefits, while reducing overall power consumption. This enables designers to pack more functionality into a smaller form factor, facilitating the development of smaller electronic devices.
JEDEC Committee JC-63 for Multiple Chip Package is working to enable the MCP market. Manufacturers likely to produce chips to be sold in an MCP form have common ballouts on the chips being defined in JEDEC, thereby facilitating the use of multiple vendors’ devices in one MCP solution. JC-63 also defines MCP packages for mixed technologies.