Semiconductor memory plays an essential role in the development of countless electronic devices ranging from computers and gaming consoles to televisions and telecommunications products. JEDEC standards encompass virtually every key standard for semiconductor memory in the market today.
Due to popular demand, JEDEC has made the presentations from its DDR4 Workshops available online. With audio and slides captured at the February 2013 Workshop, each presentation is available for immediate download upon purchase. Individual sessions are $40 each, or save $60 and purchase all 9 for just $300. To order visit: http://www.jedec.org/ddr4workshop.
The per-pin data rate for DDR4 is specified as 1.6 giga transfers per second to an initial maximum objective of 3.2 giga transfers per second. With DDR3 exceeding its original targeted performance of 1.6 GT/s, it is likely that higher performance speed grades will be added in a future DDR4 update. Other DDR4 attributes tightly intertwined with the planned speed grades, enabling device functionality as well as application adoption, include: a pseudo open drain interface on the DQ bus, a geardown mode for 2,667 MT/s per DQ and beyond, bank group architecture, internally generated VrefDQ and improved training modes.
|LOW POWER DOUBLE DATA RATE 4 (LPDDR4)||JESD209-4A||Nov 2015|
|Annex E, R/C E, in 260-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM SODIMM Design Specification||MODULE 4.20.25.E||Sep 2015|
|LRDIMM DDR3 MEMORY BUFFER (MB)||JESD82-30||Oct 2014|
|Annex F, R/C F, in 260-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM SODIMM Design Specification||MODULE 4.20.25.F||Aug 2014|
|204-Pin DDR3 SDRAM Unbuffered SODIMM Design Specification||MODULE 4.20.18||May 2014|
|Registration - 240 Pin DDR3 DIMM (Dual Inline Memory Module) Family with 1.00 mm pitch. DIM||MO-269J||Apr 2014|
|Registration - 204 Pin DDR3 SODIMM w/ 0.60 mm Pitch. DIM||MO-268E||Mar 2014|
|SPD Annex K - Serial Presence Detect (SPD) for DDR3 SDRAM Modules (Release 6)||SPD4_01_02_11||Feb 2014|
|Addendum No. 3 to JESD79-3 - 3D Stacked SDRAM||JESD79-3-3||Dec 2013|
|DDR4 SDRAM STANDARD||JESD79-4A||Nov 2013|
|JEDEC-wide Meeting (JC-11,13,14,16,40,42,45,63,64)||6 - 10 Jun 2016|
|JC-16,40,42,45,63,64||5 - 9 Dec 2016|
|JC-16,40,42,45,63,64||6 - 10 Mar 2017|
|JC-16,40,42,45,63,64||5 - 9 Jun 2017|
|JC-16,40,42,45,63,64||28 - 1 Sep 2017|