JEDEC committees are responsible for a broad spectrum of ongoing standards development work related to 3D-ICs. As the dominant provider of free and open standards for high volume semiconductor applications including device, package, reliability and test standards, JEDEC is uniquely positioned to develop the standards needed to move this game-changing technology into high volume product applications.
3D is particularly suited for combinations of memory with other memory or logic, and since JEDEC has led the development of functional, interface and packaging standards for many generations from the very beginning of semiconductor memory including DRAM, FLASH and SRAM, it has the expertise to enable 3D standards for stacked devices and mixed technology ICs. “JEDEC standards will allow high volume products to take advantage of this exciting technology,” notes Subu Iyer, IBM Fellow responsible for 3D integration at IBM.
To meet industry demands for increased levels of integration as well as improved performance, bandwidth, latency, power, weight and form factor, microelectronics manufacturers are implementing three dimensional (3D) chip stacking utilizing Through Silicon Via (TSV) chip to chip interconnects.
Several JEDEC committees and task groups covering a broad range of technologies have invested years of effort in laying the groundwork for 3D-IC standards. With interest in 3D-IC technology reaching an all-time high, now is the time for companies to get involved and influence both the near-term and strategic future standards needed to enable and grow the market for 3D-ICs.
The Solid State Memories Committee (JC-42) has a variety of subcommittees and task groups that have been working for several years on a variety of 3D standards.
The JC-42.2 Subcommittee is working on “Tile” memory applications utilizing TSV technology to enable direct die stacking and TSV connection of memory die on other devices such as specific ASICs. The TSV Tile Memory task group expects to publish a standard to enable a broad range of applications to take advantage of the economies of scale provided by standardized technology.
The DRAM Memories Subcommittee (JC-42.3) has been working since June 2008 on definitions of standardized 3D memory stacks for DDR3 that provide power and performance benefits a full generation ahead of conventional technology. The 3D Stacked SDRAM task group is currently putting the finishing touches on the respective 3DS DDR3 Addendum to JESD79-3, expected to be published in mid-2012. The 3DS DDR4 DRAM addendum is also making good progress and is expected to be published at about the same time at the DDR4 SDRAM Device base standard. The DDR4 SDRAM 3DS Addendum will allow up to eight memory dies to be stacked in one package with each pin presenting only a single electrical load to the system. The entire stack of devices can be addressed with a single chip-select signal and will enable up to 128 banks of SDRAM memory in a single device.
The High Bandwidth Memory (HBM) task group has been moved to the JC-42.3 Subcommittee and has been working since March 2011 on defining a standard that leverages Wide I/O and TSV technologies to deliver products ranging from 128GB/s to 256GB/s. The HBM task group is defining support for up to 8-high TSV stacks of memory on a data interface that is 1024-bits wide. This interface is partitioned into 8 independently addressable channels to support a 32-byte minimum access granularity per channel. The subcommitee anticipates publication in mid-2013.
The Low Power Memories Subcommittee (JC-42.6) has published a standard for Wide I/O Mobile DRAM with TSV interconnect stacked on System on a Chip (SoC) Application Processors. Download JESD229 Wide I/O Single Data Rate (SDR) free of charge.
Multiple Chip Packages Committee
The Multiple Chip Packages Committee (JC-63) is currently developing mixed technology pad sequence and device package standards to enable SRAM, DRAM and Flash memory to be combined into a single package that may also contain processor(s) and other devices. Other MCP standards are available; refer to the JC-63 Committee page for more information.
Quality & Reliability
The Silicon Devices Reliability Qualification & Monitoring Subcommittee (JC-14.3) has been working on reliability interactions of 3D stacks and has released JEP158
: 3D Chip Stack with Through-Silicon Vias (TSVS): Identifying, Understanding and Evaluating Reliability Interactions. In addition, reliability test methods developed by JC-14.1 and JC-14.2 and quality documents developed by JC-14.4 are applicable to 3D-IC packaged and unpackaged evaluations and qualifications.
The Mechanical Standardization Committee (JC-11) has been working since June 2010 on WideIO Mobile Memory package outline standardization, including an active Task Group focused on Design Guide and MO creation.
Participate - Join JEDEC
JEDEC Committees and Task Groups meet regularly and invite technology and product developers from interested companies and organizations worldwide to participate by becoming a JEDEC member today